Packaging technology for the NEC SX-3/SX-X Supercomputer

Abstract

The LSI packaging technique utilized for the SX-3/SX-X is outlined. The VLSI chip is packaged in a chip carrier called the flipped tape-automated-bonding carrier (FTC), which has 604 input/output (I/O) bumps arranged in a matrix configuration on its bottom surface. The high-density multichip package (MCP) consists of a multilayer substrate (MLS) with a maximum of 100 FTCs and 11540 I/O pins. The MLS is a 225-mm*225-mm, 5.5-mm-thick ceramic substrate with a fine-line multilayer wiring part consisting of seven polyimide insulative layers and eight conductor layers. A multilayer board mounts the MCPs with novel zero insertion force (ZIF) connectors, and high-speed coaxial cablings are used for the interconnection system. Adoption of the ZIF-MCP connector allows insertion of multiple pin sat one stroke and high-speed interconnection. A sophisticated and reliable water cooling technique is used to cool the package efficiently. Water circulates from a cooling unit (CLU) to liquid cooling modules (LCM) that cover the MCPs. This system has a cooling capacity of up to 4-kW heat dissipation of the MCP.<>