Micro and Nanostructures最新文献

{"title":"Recent developments in AlGaN/GaN MOSHEMTs for future high power RF electronics: A review","authors":"K. Ratna,&nbsp;J. Ajayan,&nbsp;B. Mounika","doi":"10.1016/j.micrna.2025.208339","DOIUrl":"10.1016/j.micrna.2025.208339","url":null,"abstract":"<div><div>AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) have emerged as strong candidates for high-reliability applications in power electronics and radio-frequency systems. This review presents a comprehensive analysis of recent developments in MOSHEMT technology, emphasizing innovations in gate dielectric materials, device architectures, and fabrication techniques aimed at improving long-term operational stability. The integration of high-k and ferroelectric dielectrics has demonstrated enhanced gate control, reduced leakage, and improved threshold voltage tuning. Architectural modifications such as gate recessing, tri-gate structures, and dual-channel configurations have significantly contributed to performance metrics, including ON-resistance (R_ON), transconductance (g_m), and breakdown voltage (V_BR). The review further addresses reliability challenges posed by thermal stress, bias-induced degradation, and radiation exposure, outlining strategies such as surface passivation, optimized annealing, and material selection to mitigate failure mechanisms. The advancements summarized in this work underscore the growing potential of AlGaN/GaN MOSHEMTs in delivering high-efficiency, robust solutions for modern microelectronic systems operating in demanding environments.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208339"},"PeriodicalIF":3.0,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Vertically stacked GAA–SOI FinFET-based CFETs for low-power and RF applications: DC, QSCV, and AC performance analysis","authors":"Ghazala Shakeel,&nbsp;Gopi Krishna Saramekala","doi":"10.1016/j.micrna.2025.208347","DOIUrl":"10.1016/j.micrna.2025.208347","url":null,"abstract":"<div><div>In this work, a novel Complementary Field-Effect Transistor (CFET) is proposed, featuring a vertically stacked configuration of an n-type Silicon-on-Insulator FinFET (SOI-FinFET) and a p-type Gate-All-Around (GAA) Nanosheet transistor with a shared gate. The proposed device is analyzed using the Silvaco TCAD tool to evaluate key performance metrics, such as ON current (Ion), OFF current (Ioff), threshold voltage (Vth), subthreshold swing (SS), gain, cut-off frequency, and quasi-static capacitance-voltage (C–V) characteristics. A critical aspect of this study is the introduction of an oxide layer between the SOI-FinFET (nMOS) and GAA (pMOS) transistors, which effectively minimizes parasitic capacitance and enhances overall performance. Simulation results show that the proposed CFET structure achieves superior SS, increased Ion, and reduced Ioff, along with excellent scalability compared to conventional counterparts. These advantages render the novel ultra-short channel CFET highly suitable for high-performance, low-power electronic applications. The proposed structure is anticipated to improve the performance of future sub-nanometer devices, potentially replacing traditional CMOS technology.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208347"},"PeriodicalIF":3.0,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145057167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of superjunction MOSFET dynamic performance using Si1−xGex strained silicon","authors":"Yiming Zhang ,&nbsp;Ran Tao ,&nbsp;Dawei Gao","doi":"10.1016/j.micrna.2025.208341","DOIUrl":"10.1016/j.micrna.2025.208341","url":null,"abstract":"<div><div>Although Si_{1−<em>x</em>}Ge_<em>x</em> strain engineering has been extensively developed in low-voltage CMOS technology, its application in superjunction (SJ) power MOSFETs remains insufficiently investigated. This work demonstrates two synergistic advantages of integrating Si_{1−<em>x</em>}Ge_<em>x</em> in SJ architectures: (1) carrier mobility enhancement through stress-modulated effective mass reduction, and (2) heterojunction band engineering for improved body diode characteristics. A novel SJ MOSFET featuring a Si_{1−<em>x</em>}Ge_<em>x</em> active region atop P/N pillars is proposed and analyzed via TCAD simulations. This design leverages stress effects at the Si_{1−<em>x</em>}Ge_<em>x</em>/Si interface on carrier mobility and band structure, significantly enhancing reverse recovery performance without compromising forward conduction performance. TCAD simulations analyze the effects of Ge contents variation on interface stress and device static/dynamic characteristics. Significant interfacial stress occurs at the Si_{1−<em>x</em>}Ge_<em>x</em>/Si heterojunction, increasing with Ge content <em>x</em>. This stress significantly modulates carrier mobility and bandgap. However, excessive Ge causes a significant increase in defect density within the Si_{1−<em>x</em>}Ge_<em>x</em> layer, and stress relaxation induces high-density interface defects, severely degrading leakage current and breakdown voltage. Comprehensive trade-off analysis identifies an optimal Ge composition (<em>x</em> = 0.6), yielding reverse recovery charge <em>Q</em>_<em>rr</em> = 0.87 μC cm² and conduction loss <em>E</em>_<em>on</em> = 15.34 μJ cm². These values represent 78.7 % lower <em>Q</em>_<em>rr</em> and 37.3 % lower <em>E</em>_<em>on</em> than conventional Si-based SJ MOSFETs. These advancements demonstrate significant potential of Si_{1−<em>x</em>}Ge_<em>x</em> SJ MOSFETs for high-frequency and high-voltage applications.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208341"},"PeriodicalIF":3.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DC/RF performance analysis of vertical Nnanowire FET with dielectric pocket and stacked oxide configuration","authors":"Rajat Gulghane ,&nbsp;Archana Pandey ,&nbsp;Swaroop Kumar Macherla ,&nbsp;Kavicharan Mummaneni ,&nbsp;Ekta Goel","doi":"10.1016/j.micrna.2025.208337","DOIUrl":"10.1016/j.micrna.2025.208337","url":null,"abstract":"<div><div>As transistors shrink, the gate oxide must become extremely thin. This leads to a quantum mechanical effect called direct tunneling. This creates a significant gate leakage current which is a major source of power consumption and heat in modern chips. Instead of a single thin layer of Silicon Dioxide (SiO₂), a stacked oxide and dielectric pocket are used for stronger control of the channel. Hence, this manuscript presents an analysis of a Vertical Nanowire FET device featuring a stacked oxide and dielectric pocket configuration. It demonstrates that the device exhibits improved performance characteristics compared to previously reported data. In this work, the proposed device has been evaluated concerning conventional VNWFET and Dielectric Pocket VNWFET (DP-VNWFET). The device's DC analysis has been conducted, analyzing DC performance metrics such as I_ON, I_OFF, I_ON/I_OFF ratio, subthreshold swing (SS), and threshold voltage (V_t) in comparison to existing reported work. Furthermore, the AC/RF performance of the device has been evaluated based on performance metrics such as transconductance (g_m), output transconductance (g_d), intrinsic gain, gain-bandwidth product (GBP), cutoff frequency, and transconductance frequency product (TFP). The proposed device exhibits excellent characteristics and proves to be highly suitable for both current and emerging technological advancements.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208337"},"PeriodicalIF":3.0,"publicationDate":"2025-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-performance JLCSG MOSFET biosensor considering quantum confinement for multi-region neutral biomolecule species detection","authors":"Qing-an Ding,&nbsp;Shengyuan Fan,&nbsp;Fangfang Ning,&nbsp;Jianyu Li,&nbsp;Bing Chen,&nbsp;Yandong Peng,&nbsp;Fei Wang,&nbsp;Dasheng Diao,&nbsp;Yuhua Gao","doi":"10.1016/j.micrna.2025.208333","DOIUrl":"10.1016/j.micrna.2025.208333","url":null,"abstract":"<div><div>This work demonstrates a high-performance dielectrically modulated biosensor based on short-channel junctionless cylindrical surrounding-gate MOSFET with excellent gate control capability to efficiently suppress the short channel effects (SCEs). Particularly, a novel analytical model incorporating both depleted and free charges has been developed, which significantly enhances detection precision by ensuring high sensitivity and stability across diverse operating regions. Within each region, the quantum confinement effects (QCEs) are rigorously evaluated by solving the Schrödinger equation, revealing the quantized eigenenergies and the corresponding electron density distribution in small-radius channels. Furthermore, the shift in the lowest eigenenergy is leveraged to define a sensitivity metric that directly probes the quantum-level perturbations from biomolecule binding, which effectively amplifies the sensing signal and improves predictive accuracy. Afterwards, the analysis identifies non-ideal incomplete biomolecule hybridization and interface trap charges (ITCs) as the primary sources of performance degradation, providing a clear path for their targeted mitigation. By optimizing the structural parameters guided by key performance metrics and timing response constraints, the proposed device exhibits a superior threshold voltage sensitivity of 0.383 and an exceptionally high current switching ratio of 1 × 10¹³. Therefore, this study is highly suitable for neutral biomolecule detection, even offering robust guidance for the design and multifunctional application of biosensors.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208333"},"PeriodicalIF":3.0,"publicationDate":"2025-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Graphene-boron nitride-transition metal dichalcogenides heterostructure based MISFET","authors":"Shubham Rahi ,&nbsp;Rajender Kumar ,&nbsp;Sapna Singh ,&nbsp;Prasanna Misra ,&nbsp;Ganesh C. Patil ,&nbsp;Trupti Ranjan Lenka ,&nbsp;Ankur Solanki ,&nbsp;Anurag Chauhan ,&nbsp;Balwinder Raj ,&nbsp;Pinku Nath ,&nbsp;Sudhanshu Choudhary","doi":"10.1016/j.micrna.2025.208320","DOIUrl":"10.1016/j.micrna.2025.208320","url":null,"abstract":"<div><div>Stacking of 2D materials has opened new dimensions in the area of Nano-electronics as both optical and electronic properties of the material change significantly by altering number of layers stacked and materials stacked. A vander waal's (vdWH) heterostructure based metal insulator semiconductor field effect transistor (MISFET) with various channel materials like MoS₂, MoSe₂ and WS₂ is investigated to assess the differences in electronic properties at both material and device levels. The results suggest that amongst all transition metal dichalcogenides (TMDs) channel materials considered, WS₂ has lowest effective mass (for both electron and hole) and highest I_dsat (saturation current) ∼9.216 × 10⁻⁵ Å/ <span><math><mrow><mi>μ</mi></mrow></math></span> m which suggests the use of WS₂ in making high performance Field Effect Transistors. However, because bulk WS₂ is an indirect bandgap material, it is unsuitable for the fabrication of optical devices. This limitation is addressed by using monolayer WS₂, which possesses a direct bandgap. The values of I_dsat for MoS₂ and MoSe₂ based devices are obtained as ∼4.37 × 10⁻⁵ A/ <span><math><mrow><mi>μ</mi></mrow></math></span> m and ∼2.323 × 10⁻⁵ A/ <span><math><mrow><mi>μ</mi></mrow></math></span> m. Furthermore, WS₂ as channel material has lowest threshold voltage ∼1 V in comparison to ∼1.1 V and ∼1.2 V for MoS₂ and MoSe₂ based transistors.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208320"},"PeriodicalIF":3.0,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145010716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel thermal network model and electro-thermal coupling study for NSFETs and CFETs considering thermal crosstalk","authors":"Tianci Miao ,&nbsp;Qihang Zheng ,&nbsp;Yangyang Hu ,&nbsp;Xiaoyu Cheng ,&nbsp;Jie Liang ,&nbsp;Liang Chen ,&nbsp;Aiying Guo ,&nbsp;Jingjing Liu ,&nbsp;Kailin Ren ,&nbsp;Jianhua Zhang","doi":"10.1016/j.micrna.2025.208322","DOIUrl":"10.1016/j.micrna.2025.208322","url":null,"abstract":"<div><div>As the process node of logic integrated circuits continues to shrink to chase the Moore's Law, nanosheet field effect transistors (NSFETs) and complementary FETs (CFETs) become candidates for the 3 nm and sub-nanometre nodes. However, due to the shrinking device size, self-heating and inter-device thermal crosstalk of NSFETs and CFETs become more severe, leading to degradation of on-state current, threshold voltage shift, and reduced reliability. It is of great significance to accurately calculate the self-heating and thermal crosstalk of devices and to investigate their influences on the electrical and thermal characteristics of logic gates. In this work, a novel thermal network model considering the thermal crosstalk of neighboring devices is proposed, which can accurately calculate the self-heating and thermal crosstalk by introducing a dummy network. The electrical and thermal characteristics of NSFETs and CFETs are compared, and it is found that CFETs suffer more severe self-heating and thermal crosstalk. The electro-thermal characteristics of inverters, logic gates and ring oscillators composed of NSFETs and CFETs are further investigated. Compared with NSFETs, logic gates and ring oscillators composed of CFETs are more seriously affected by self-heating and should be given extra attention. The thermal network model proposed in this work can be further used to study the thermal optimization strategy of devices and circuits to enhance the electrical performances, achieving the design technology co-optimizations (DTCO).</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208322"},"PeriodicalIF":3.0,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145010713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of oxygen in the annealing treatment of Al2O3/β-Ga2O3 MOS capacitors","authors":"Yuxiang Lin ,&nbsp;Song Du ,&nbsp;Hao Long","doi":"10.1016/j.micrna.2025.208321","DOIUrl":"10.1016/j.micrna.2025.208321","url":null,"abstract":"<div><div>Gallium oxide (Ga₂O₃) has emerged as a highly promising material for high-power electronic applications, owing to its ultra-wide bandgap, exceptional breakdown electric field, and low conduction losses. However, interfacial defects between Ga₂O₃ and the gate dielectric critically undermine device performance, highlighting the urgent need for robust interface engineering strategies. This study investigated the effect of annealing treatment on the interfacial and dielectric properties of Al₂O₃/β-Ga₂O₃ metal-oxide-semiconductor (MOS) capacitors. A comprehensive analysis of interface, border, and bulk traps revealed that O₂ annealing markedly improved both interface passivation and dielectric properties. The presence of active oxygen species promoted Ga–O bond formation, suppressing surface dangling bonds and oxygen vacancies, and thereby enabling the growth of a high-quality dielectric layer. In contrast, while N₂ annealing reduced surface contaminants, its lack of active oxygen species limited defect passivation. These results underscored the pivotal role of oxygen in thermal treatments and offered a practical route toward high-performance Ga₂O₃-based power devices.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208321"},"PeriodicalIF":3.0,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144926557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Neuromorphic integration and real-time programmability of temporally-coded phase-change plasmonic platforms for on-chip multilevel optical memory and adaptive logic systems","authors":"Viyat Varun Updhay ,&nbsp;N. Nagabhooshanam ,&nbsp;Sharad Rathore ,&nbsp;Madan Lal ,&nbsp;A.C. Santha Sheela ,&nbsp;D. Beulah ,&nbsp;A. Rajaram","doi":"10.1016/j.micrna.2025.208317","DOIUrl":"10.1016/j.micrna.2025.208317","url":null,"abstract":"<div><div>This research reports the operation, architecture of a neuromorphic-compatible and real-time, programmable optical memory device, through temporally encoded femtosecond laser excitation of phase-change plasmonic nanomaterials. High-quality Ge₂Sb₂Te₅ (GST) thin films with sub-nanometer roughness (0.46–0.61 nm) were fabricated over rigid substrates using RF-magnetron sputtering that provided a smooth phase transition. Bowtie antennas produced under electron beam lithography showed a local maximum electric field enhancement of |E/E₀| ≈ 18.2, with resonance peaks at wavelengths of ∼1270 nm. The amorphous, partially crystalline, and crystalline state transitions using a femtosecond laser, leading to reflectance modulations of 8.5–35.2 percent, were used to achieve 2-bit memory encoding (00–11) on a stable basis. Electrical characterization showed single-crystal conductivity deviations of more than four orders between the states, with switching times less than 180 ps measured by pump-probe. The finite-Difference Time-Domain (FDTD) and COMSOL simulations verified the photothermal triggered efficient activation and interface-limited crystallization with an Avrami exponent of ∼2.0 and the thermal hotspot temperature of ∼465 K. The write/erase drift was less than 5 percent at over 10,000 write/erase cycles, and optical logic gates (AND, OR, XOR) success rates of 97–100 percent were obtained. This system integrates memory and logic on one nanoscale platform and is reconfigurable, high-density, ultrafast, and low-power, with potential scalability to in-memory photonic computing and neuromorphic applications.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208317"},"PeriodicalIF":3.0,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145020181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of gold nanoparticles on resistive type nickel oxide based MEMS gas sensor properties","authors":"Аnastasia Kondrateva ,&nbsp;Ivan Komarevtsev ,&nbsp;Ilya Lazdin ,&nbsp;Yakov Enns ,&nbsp;Alexey Kazakin ,&nbsp;Elizaveta Fedorenko ,&nbsp;Alexandr Shakhmin ,&nbsp;Valentina Andreeva ,&nbsp;Maxim Mishin ,&nbsp;Platon Karaseov","doi":"10.1016/j.micrna.2025.208318","DOIUrl":"10.1016/j.micrna.2025.208318","url":null,"abstract":"<div><div>The technology to produce hydrogen sulphide sensor with a sensitive layer based on nickel oxide on a silicon chip is presented. Response of the sensor to H₂S in concentrations from 1 to 70 ppm at 190 °C operating temperature is investigated. Modification of NiO film with gold nanoparticles (GNPs) significantly improves sensitivity level. The sensing layer made of NiO embedded with GNPs shows five times higher response and improved response time compared to pure nickel oxide one. The response time under 70 ppm H₂S in Ar exposure is ∼5 s and the recovery time is ∼28 min. The enhanced sensitivity of NiO embedded with GNPs is attributed to (i) the increased crystallinity of NiO grown over the gold nanoparticles and (ii) the spillover effect of GNPs in NiO. MEMS technology used to produce the sensor chip with thin active layers makes it possible to drastically reduce the energy consumption of the sensor.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"207 ","pages":"Article 208318"},"PeriodicalIF":3.0,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144932085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}