Ziyi He;Dinusha Herath Mudiyanselage;Dawei Wang;Bingcheng Da;Junzhe Xie;Michel Khoury;Yuji Zhao;Houqiang Fu
{"title":"Electrical and Reliability Study of GaN E-Mode MISHEMTs With Two-Step Etching Gate Recess","authors":"Ziyi He;Dinusha Herath Mudiyanselage;Dawei Wang;Bingcheng Da;Junzhe Xie;Michel Khoury;Yuji Zhao;Houqiang Fu","doi":"10.1109/TMAT.2025.3606438","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3606438","url":null,"abstract":"In this paper, we developed a simple gate recess etching technique for the fabrication of GaN E-mode HEMT. A systematic comparison between the high-power etching and high-low-power etching gate recessed E-mode GaN HEMT has been carried out. The device with high-low power etching showed increased on-current, reduced gate leakage current and threshold voltage dispersion, and reduced hysteresis. The device with high-low power etching showed an improved interface between dielectric and recessed gate with an interface trap density of 1.2 × 10<sup>12</sup> cm<sup>−2</sup>⋅eV<sup>−1</sup> to 2.2 × 10<sup>12</sup> cm<sup>−2</sup>⋅eV<sup>−1</sup>, which is about half of the value in the high power etching device. Gate step-stress testing and positive gate-bias stress testing showed an improved gate robustness, and reduced threshold voltage shift resulting from reduced SiN<sub>x</sub>/GaN interface traps for high-low-power etching MISHEMT. Time-dependent dielectric breakdown (TDDB) testing showed its increased gate voltage of 5 V for maintaining a 10-year lifetime compared to 4.5 V for the high-power etching device. This work demonstrated and analyzed an easy-to-implement approach for realizing high-performance low interface trap E-mode GaN MISHEMT.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"108-112"},"PeriodicalIF":0.0,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bingcheng Da;Dinusha Herath Mudiyanselage;Dawei Wang;Ziyi He;Junzhe Xie;Houqiang Fu
{"title":"Ultrawide Bandgap AlN Trench Metal-Oxide-Semiconductor Transistors (MOSFETs) on Single-Crystal AlN Substrates","authors":"Bingcheng Da;Dinusha Herath Mudiyanselage;Dawei Wang;Ziyi He;Junzhe Xie;Houqiang Fu","doi":"10.1109/TMAT.2025.3601062","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3601062","url":null,"abstract":"This work reports the demonstration of AlN trench metal-oxide-semiconductor transistors (MOSFETs) on single-crystal AlN substrates, where the impacts of gate trench depth were investigated. It was found that the device with a deeper gate trench showed enhanced output characteristics with increased on/off ratio of >600 by ∼20 times, improved maximum transconductance of 3.1 μS/mm by ∼2 times, and higher maximum drain current of 47 μA/mm by ∼1.5 times, compared with the device with a shallow gate trench. Compared with the reported AlN MOSFETs on sapphire substrates, the AlN-on-AlN device exhibited ∼10 times higher drain current, ∼15 times larger transconductance, and ∼2 times larger average breakdown electric field of >1MV/cm. These results will benefit the future development of high-performance AlN power electronics.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"103-107"},"PeriodicalIF":0.0,"publicationDate":"2025-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144934455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Vat Photopolymerization of Al2O3/Borosilicate Glass Low Temperature Co-Fired Ceramic Substrates With Integrated Micropore Patterning Device","authors":"Yizhen Chu;Yujuan Zhou;Mingyong Jia;Qianshun Cui;Haiyuan Shi;Zhifeng Huang;Fei Chen","doi":"10.1109/TMAT.2025.3598753","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3598753","url":null,"abstract":"Low temperature co-fired ceramics (LTCC) have garnered significant attention due to their exceptional electrical and thermal properties. While the traditional tape casting method for preparing LTCC substrates yields high density, it is constrained by limited geometric freedom and a complex process, making it less suitable for contemporary demands. In this study, we employ vat photopolymerization 3D printing technology to fabricate alumina/borosilicate glass composite LTCC systems and introduce a microporous structure design on the substrate. This innovation simplifies the traditional punching step, enhancing both productivity and reliability. We formulated LTCC slurry suitable for vat photopolymerization and examined the thermal conductivity and dielectric properties of the sintered parts. The findings reveal that samples held at 750 °C for 30 minutes achieved the highest densities, exhibiting a thermal conductivity of 3.63 W·m<sup>−1</sup>·K<sup>−1</sup>, a relative dielectric constant of 13.09, and the lowest dielectric loss (7.9 × 10<sup>−3</sup>). We successfully realized microporous printing on LTCC substrates, achieving microporous structures with an actual diameter of 132 μm. Additionally, we verified the compatibility of substrates with silver co-firing, observing a robust bond between the silver layer and the LTCC layer. This study underscores the potential of vat photopolymerization for LTCC applications.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"95-102"},"PeriodicalIF":0.0,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144916326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BEOL-Compatible 5.6 nm Ultrathin HZO With Molybdenum Nitride Electrode and IN2O3 Channel Devices for Enhanced Ferroelectricity and Reliability","authors":"Li-Cheng Teng;Yu-Che Huang;Shin-Yuan Wang;Yu-Hsien Lin;Chao-Hsin Chien","doi":"10.1109/TMAT.2025.3586809","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3586809","url":null,"abstract":"In this letter, we have successfully fabricated a metal-ferroelectricity-metal (MFM) capacitor of an ultrathin 5.6 nm HZO and ultrathin In<sub>2</sub>O<sub>3</sub> back gate devices in a back-end-of-line (BEOL) compatible process. By proposing a novel atomic layer deposition (ALD) scheme and an alternative bottom electrode treatment, the MoN-HZO sample shows an average 2Pr value of 64 μC/cm<sup>2</sup> (with a standard deviation of 0.52) and high endurance (△2Pr/2Pr<sub>pristine</sub> ≈2% from pristine to 10<sup>10</sup> cycles). The MoN–HZO stack integrated with an ultrathin In<sub>2</sub>O<sub>3</sub> back gate exhibits a memory window (MW) greater than 2.5 V and excellent endurance and data retention characteristics. With a maximum process temperature of 400°C, our approach meets the stringent requirements for Back-End-of-Line (BEOL) integration.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"90-94"},"PeriodicalIF":0.0,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144704968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Call for Papers: Special Issue of IEEE Transactions on Electron Devices on Reliability of Advanced Nodes","authors":"","doi":"10.1109/TMAT.2025.3583512","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3583512","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11053704","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tunable Density-of-States in Chromium Oxide Thin Films via Room Temperature Laser Ablation","authors":"Angel Regalado-Contreras;Wencel de la Cruz","doi":"10.1109/TMAT.2025.3581508","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3581508","url":null,"abstract":"Chromium oxide thin films were deposited at room temperature, via reactive laser ablation under varying O<sub>2</sub> pressures and analyzed using in-situ X-ray Photoelectron Spectroscopy. Cr 2p spectra exhibited spin-orbit splitting, with peak separations ranging from 9.2 to 9.5 eV. Cr<sup>3+</sup>, and Cr<sup>4+</sup> states were identified, with 2p<sub>3/2</sub> binding energies between 576.8 and 582.5 eV. Quantitative analysis confirmed that lower O<sub>2</sub> pressures favored Cr<sub>2</sub>O<sub>3</sub> growth, while higher pressures promoted CrO<sub>2</sub>. Near-Fermi-level spectra revealed significant Density-Of-States modulation, with the Valence Band Maximum shifting from 1.25 to 3.3 eV. A direct correlation between O<sub>2</sub> pressure and electronic structure was established.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"86-89"},"PeriodicalIF":0.0,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144606251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transferable Freestanding Varactor Based on a Membrane Stack for Microwave Application","authors":"Yating Ruan;Philipp Komissinskiy;Alexey Arzumanov;Holger Maune;Lambert Alff","doi":"10.1109/TMAT.2025.3580484","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3580484","url":null,"abstract":"This work demonstrates the fabrication and characterization of a freestanding oxide varactor membrane designed for integration onto silicon substrates. An epitaxial varactor heterostructure composed of a 1% Mn-doped Ba<inline-formula><tex-math>$_{0.5}$</tex-math></inline-formula>Sr<inline-formula><tex-math>$_{0.5}$</tex-math></inline-formula>TiO<inline-formula><tex-math>$_{3}$</tex-math></inline-formula> dielectric layer and a <inline-formula><tex-math>$rm {SrMoO}_{3}$</tex-math></inline-formula> conductive layer was grown using pulsed laser deposition on a water-soluble sacrificial layer <inline-formula><tex-math>$rm {Sr_{3}Al_{2}O_{6}}$</tex-math></inline-formula>. After the lift-off process, the varactor heterostructure was successfully transferred onto a silicon substrate. Structural analysis confirms the high crystallinity and strain relaxation of the heterostructure after transfer. Electrical measurements reveal high tunability (<italic>n</i>=1.7) at 120 V/<inline-formula><tex-math>$mu rm {m}$</tex-math></inline-formula>, a quality factor exceeding 100 at 1 MHz, and a low leakage current density well below 5 <inline-formula><tex-math>$text{A/m}^{2}$</tex-math></inline-formula>. This approach overcomes the challenges of direct oxide growth of epitaxial varactor heterostructures on silicon, such as lattice mismatch and chemical incompatibility. These results validate the potential of freestanding varactor membranes for agile microwave and RF applications, offering a scalable route for high-performance, multifunctional devices with low energy consumption in next-generation telecommunications and wireless networks.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"80-85"},"PeriodicalIF":0.0,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11039081","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144557714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved Performance of Yttrium Oxide-Based Memristor Through TiN Electrodes and Device Scaling for Neuromorphic and Pattern Recognition","authors":"Sanjay Kumar;Shalu Rani","doi":"10.1109/TMAT.2025.3579714","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3579714","url":null,"abstract":"Herein, we present a CMOS-compatible fabrication process, in-depth materials, and electrical analysis of yttrium oxide (Y<sub>2</sub>O<sub>3</sub>)-based memristive devices having a device size of 100 μm<sup>2</sup>. The fabricated devices exhibit improved performance by incorporating TiN electrodes and device scaling and efficiently emulate the various low-power neuromorphic and pattern recognition tasks. The fabricated memristive devices exhibit stable bipolar resistive switching behavior with an excellent endurance beyond 50,000 cycles and retention properties exceeding 10<sup>6</sup> s by maintaining a very high ON/OFF ratio of 10<sup>4</sup>. Additionally, the fabricated devices show remarkable stability in the device switching voltages under cycle-to-cycle (C2C) and device-to-device (D2D) wherein, the coefficient of variability (<italic>C</i><sub>V</sub>) in the device switching voltages in C2C and D2D is 4.95% and 11.39%, respectively. Moreover, the fabricated devices efficiently emulate the synaptic response by emulating potentiation, depression, paired-pulse facilitation (PPF), and paired-pulse depression (PPD) and also exhibit the device conductance tunability under the variations in the pulse width as similar to the biological synapse counterpart. Furthermore, the fabricated devices efficiently show the pattern recognition task by achieving an accuracy of 88.2% for the handwriting MNIST dataset. Therefore, the present work opens a new horizon in the field of miniaturized artificial synapses and neuromorphic computing to perform various operations.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"72-79"},"PeriodicalIF":0.0,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Call for Papers: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TMAT.2025.3562290","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3562290","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970663","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143856185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IEEE Electron Devices Society","authors":"","doi":"10.1109/TMAT.2025.3561623","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3561623","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10967368","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}