Electrical and Reliability Study of GaN E-Mode MISHEMTs With Two-Step Etching Gate Recess

Abstract

In this paper, we developed a simple gate recess etching technique for the fabrication of GaN E-mode HEMT. A systematic comparison between the high-power etching and high-low-power etching gate recessed E-mode GaN HEMT has been carried out. The device with high-low power etching showed increased on-current, reduced gate leakage current and threshold voltage dispersion, and reduced hysteresis. The device with high-low power etching showed an improved interface between dielectric and recessed gate with an interface trap density of 1.2 × 10¹² cm⁻²⋅eV⁻¹ to 2.2 × 10¹² cm⁻²⋅eV⁻¹, which is about half of the value in the high power etching device. Gate step-stress testing and positive gate-bias stress testing showed an improved gate robustness, and reduced threshold voltage shift resulting from reduced SiN_x/GaN interface traps for high-low-power etching MISHEMT. Time-dependent dielectric breakdown (TDDB) testing showed its increased gate voltage of 5 V for maintaining a 10-year lifetime compared to 4.5 V for the high-power etching device. This work demonstrated and analyzed an easy-to-implement approach for realizing high-performance low interface trap E-mode GaN MISHEMT.