IEEE Open Journal of the Solid-State Circuits Society最新文献

{"title":"A Temperature-Agnostic 18-MSPS, 12-bit SAR ADC Operating From 50 to 400 K for Space Instrumentation","authors":"Rui Xu;Peter R. Kinget","doi":"10.1109/OJSSCS.2026.3729530","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3729530","url":null,"abstract":"Space instrumentation is typically placed in a shielded “hot box” to protect against extreme-temperature variations, but this compromises size, weight, and power (SWaP). Unshielded instruments on the moon’s surface must operate over a continuous temperature span of 50–400 K. The challenge of wide-temperature operation mostly lies in cryogenic operation due to the onset of carrier freeze-out, and we address this by focusing on the warm temperature limit where foundry-provided models are still valid. By designing at the warm temperature limit and selecting specific circuit and architectural design choices that benefit from operation at lower temperatures, we eliminate the need for cryogenic device models while achieving the full temperature range of operation. For example, we use switching circuits that rely on charge redistribution, which benefit from faster switching at colder temperatures, but at the expense of higher leakage current and reduced switching speed at warm temperatures, rather than static-biased circuits. We demonstrate this in an 18-MSPS, 12-bit ADC that maintains >65-dB SNDR and >75-dBc SFDR across the Nyquist bandwidth and the full 50–400-K temperature range without any temperature-dependent calibration or user input. This ADC is characterized continuously across the full temperature range while being temperature agnostic and achieves a competitive energy efficiency and performance among other wide-temperature ADCs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"254-270"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11674210","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149130769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on Data Converters","authors":"Sai-Weng Sin;Qiang Li","doi":"10.1109/OJSSCS.2026.3677294","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3677294","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"162-163"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11663331","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Buckbeak: A 1.2 TFLOPS/W Reconfigurable Vector/Scalar RISC-V Processor for Precision Scalable Near-Sensor Computing in 22-nm FDSOI Technology","authors":"Marco Bertuletti;Amirhossein Kiamarzi;Mattia Sinigaglia;Gianmarco Ottavi;Matteo Perotti;Giuseppe Tagliavini;Luca Benini;Davide Rossi","doi":"10.1109/OJSSCS.2026.3695835","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3695835","url":null,"abstract":"Near-sensor computing requires the concurrent execution of data-parallel and control-intensive tasks under tight latency and power constraints. Vector processors excel at data-parallel tasks, thanks to their single-instruction multiple-data (SIMD) execution model. However, scalar control-intensive processing can still saturate their instruction-fetch frontend, undermining utilization and efficiency. To address this challenge without compromising flexibility and efficiency for data-parallel computations, we present a runtime-configurable dual-core RISC-V vector processor that switches in five cycles between split mode (two independent vector engines) and merge mode (one wide vector plus a scalar programmable core). On a sensor fusion pipeline that mixes scalar-vector workloads, data parallel tasks can be executed on the wide SIMD processor, while the programmable core, decoupled from the vector engines, takes care of scalar tasks, achieving up to <inline-formula> <tex-math>$1.47times $ </tex-math></inline-formula> speedup over Split Mode. The dual-core reconfigurability allows split mode performance optimizations on homogeneous tasks with modest data parallelism, delivering up to <inline-formula> <tex-math>$1.93times $ </tex-math></inline-formula> speedup over merge mode. Implemented in GF22FDX technology, the processor delivers 10.78 GFLOPS@FP64 to 85.64 GFLOPS@FP8 peak performance (at 1 V) and 1.2 TFLOPS@FP8/W peak energy efficiency (at 0.65 V). Thanks to the vector ISA semantics and underlying architecture, Buckbeak is up to <inline-formula> <tex-math>$4times $ </tex-math></inline-formula> more energy efficient than state-of-the-art multicore accelerators implemented in the same node. The streamlined, reconfigurable design and lightweight instruction-fetch frontend yield up to <inline-formula> <tex-math>$14.5times $ </tex-math></inline-formula> better energy efficiency and <inline-formula> <tex-math>$15times $ </tex-math></inline-formula> better area efficiency compared to larger vector processors for edge-processing applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"118-128"},"PeriodicalIF":3.2,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11534185","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Time-Interleaved ADC With a Single-Step Relative-Prime-Rotation-Based Background Timing-Skew Calibration Using MAD-Averaging","authors":"Raymond Mabilangan;Bo Gao;Charlie Tahar;Woong-Taek Lim;Kyung-Hoon Lee;Michael Choi;Kent Edrian Lozada;Dong-Jin Chang;Seung-Tak Ryu","doi":"10.1109/OJSSCS.2026.3666164","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3666164","url":null,"abstract":"This article presents a fully on-chip background timing-skew calibration technique based on relative-prime rotation (RPR), which enables the simultaneous extraction of timing-skew errors. The proposed approach eliminates multistep calibration and prevents residual-skew accumulation, resulting in fast and accurate convergence. By exploiting the mean absolute difference (MAD) between the acting reference analog-to-digital converter (ADC) and its adjacent channel, the method extends the applicable bandwidth up to the Nyquist frequency without imposing restrictions on the number of channels. An 8(+1)-channel, 10-bit, 1.1-GS/s time-interleaved successive approximation register ADC (TI-SAR ADC) prototype implementing the proposed architecture was fabricated in a 28-nm CMOS process, occupying an active area of 0.16 mm2. Operating from a 1-V supply, the prototype consumes 9.5 mW and achieves 49.7-dB signal-to-noise-and-distortion ratio (SNDR) and 61.4-dB spurious-free dynamic range (SFDR) at a 1.1-GS/s sampling rate with a near-Nyquist input. The ADC attains a competitive Walden figure of merit (FoMW) of 34.7 fJ/conversion-step, with the on-chip calibration consuming only 17% of the total power.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"164-177"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11398118","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multiemission PWM Driving Circuit With Compensation for VTH Variations and I–R Drops in Micro-LED Displays","authors":"Sung-Chun Chen;Yu-Chang Chiu;Chung-Tien Chiu;Chi-Hsuan Huang;Yuan-Yu Lai;Ming-Yang Deng;Chih-Lung Lin","doi":"10.1109/OJSSCS.2026.3707782","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3707782","url":null,"abstract":"A novel mini light-emitting diode (micro-LED) driving circuit using the low-temperature polysilicon thin-film transistors (LTPS TFTs) for use in an active matrix (AM) pixel circuit for micro-LED displays is proposed. Pulsewidth modulation (PWM) with multiemission driving is utilized, and the micro-LED is operated at a high luminous efficacy point to reduce power consumption at low gray levels compared to pulse-amplitude modulation (PAM). To generate a uniform driving current for the micro-LED, variations in the threshold voltage (<inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula>) for the driving TFT are compensated by the diode-connection structure in the proposed circuit. A larger driving current can increase the current resistance in the power source line, so there is compensation for an increase in the <inline-formula> <tex-math>$V_{mathrm {DD}}~ I$ </tex-math></inline-formula>–<inline-formula> <tex-math>$R$ </tex-math></inline-formula> drop. The <inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula> variations for the control TFT and the <inline-formula> <tex-math>$V_{mathrm {DD}}$ </tex-math></inline-formula> write-in TFT are compensated to ensure a precise emission time for the micro-LED. The simulation results of the fitting models for LTPS TFTs show that the relative time shifts are less than <inline-formula> <tex-math>$0.15~mu $ </tex-math></inline-formula>s. A micro-LED panel system that uses the proposed circuit is fabricated to verify the feasibility of compensation for the proposed micro-LED driving circuit. The measurement results demonstrate that the maximum luminance error rate is 9.24% and the color deviations (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula><inline-formula> <tex-math>$mu $ </tex-math></inline-formula>v) are all below 0.011. Hence, the proposed circuit is experimentally verified to generate uniform driving currents for micro-LED pixels in the display.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"153-161"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11585819","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Clockless Wake-Up Receiver and Crystal-Less Clock Recovery Architecture for ULP EQS-HBC Nodes","authors":"Lingke Ding;Archisman Ghosh;Qi Huang;Shreyas Sen","doi":"10.1109/OJSSCS.2026.3724807","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3724807","url":null,"abstract":"Wake-up receivers (WuRXs) in energy-constrained wireless transceivers typically rely on always-on clocks and crystal oscillators for sampling, correlation, and carrier synchronization, increasing standby power, area, and system cost. Eliminating these timing references enables leakage-level idle operation but introduces challenges in achieving low-latency asynchronous wake-up and crystal-less carrier synchronization. This work presents a 65-nm CMOS first-silicon architectural proof-of-concept featuring a clockless WuRX and a crystal-less clock recovery unit (CRU) for electro-quasistatic (EQS) human-body communication (HBC) systems. The proposed WuRX adapts directly to incoming on-off keying (OOK) data without a local sampling clock, enabling leakage-level idle listening. A successful first-silicon wake-up event is demonstrated <inline-formula> <tex-math>$80~mu $ </tex-math></inline-formula>s after the start of the applied wake-up packet. Following wake-up, the proposed CRU dynamically extracts the carrier clock from the incoming data using a hybrid open- and closed-loop timing-recovery scheme, achieving measured frequency acquisition within <inline-formula> <tex-math>$80~mu $ </tex-math></inline-formula>s from CRU enable under the reported nominal measurement condition, without an external crystal reference. Measured through-body experiments demonstrate successful asynchronous wake-up and on-the-fly clock extraction using fully integrated silicon, validating the first-silicon feasibility of eliminating both always-on clocks and external frequency references in ultralow-power (ULP) HBC nodes.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"238-253"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11658710","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148986085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Review of Energy Efficient Circuits Optimized for Single-Photon Avalanche Diodes in Medical Imaging Applications","authors":"Byungchoul Park;Hyun-Seung Choi;Dongseok Cho;Hyo-Sung Park;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/OJSSCS.2025.3648964","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3648964","url":null,"abstract":"This article presents a review on energy-efficient circuits optimized for single-photon avalanche diodes (SPADs) in medical imaging applications. SPADs enable single-photon detection capability and subnanosecond timing precision, making them highly suitable for various medical applications, such as X-ray imaging, positron emission tomography (PET), and fluorescence lifetime imaging microscopy (FLIM). However, large-area SPAD-based imagers, particularly wafer-scale X-ray detectors, face challenging energy-efficiency requirements, as millions of pixels operate concurrently at high bias voltages above the breakdown voltage, leading to significant power consumption and thermal management requirements. This review highlights various SPAD structures across different fabrication processes, such as frontside illumination (FSI) process, and backside illumination (BSI) process. It also summarizes recent advances in pixel-level front-end circuits that manage the recharge of the SPAD while minimizing power consumption. Furthermore, optimized counter architectures for the SPAD pixel are discussed, with emphasis on extrapolation-based techniques that extend the dynamic range while reducing the overall power consumption of the SPAD-based detectors. By combining these techniques, energy-efficient SPAD-based detectors for medical imaging applications can be realized, where compact integration, thermal management, and patient safety are critical.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"511-523"},"PeriodicalIF":3.2,"publicationDate":"2025-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11316338","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Direct Current-to-Digital Converter IC for Luminescence-Based Detection Toward an Energy Efficient Transcutaneous Carbon Dioxide Sensor Wearable","authors":"Tuna B. Tufan;Benjamin Larkin;John McNeill;Ulkuhan Guler","doi":"10.1109/OJSSCS.2025.3646593","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3646593","url":null,"abstract":"Continuous monitoring of arterial carbon dioxide is critical for assessing respiratory function and detecting ventilation inefficiencies. Arterial blood gas analysis, the clinical gold standard, is invasive and limited to intermittent measurements in hospital settings. Transcutaneous carbon dioxide sensing offers a noninvasive alternative by measuring carbon dioxide diffusing through the skin, which strongly correlates with arterial carbon dioxide. However, conventional transcutaneous sensors require bulky bedside monitors and heating elements, making them unsuitable for wearable applications. This work presents the first integrated circuit implementation of a ratiometric time-domain dual lifetime referencing technique using a direct current-to-digital converter architecture designed for energy-efficient wearables. The proposed design achieves 0.15-nA/cnt resolution over a 30-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A input range at 88-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W power consumption. With the proposed I-DAC current-scaling technique, the system maintains a luminescence ratio error of <inline-formula> <tex-math>$le 0.5$ </tex-math></inline-formula>% across a wide input range.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"388-399"},"PeriodicalIF":3.2,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304713","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shared Switched Capacitor Multioutput Hybrid Converter for High Conversion Ratio Applications","authors":"Ratul Das;Hanh-Phuc Le","doi":"10.1109/OJSSCS.2025.3644337","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3644337","url":null,"abstract":"This work presents a shared-switched-capacitor multioutput hybrid (SSC-MoH) converter to support large conversion ratios from a 12–24 V input to three separate outputs of 0.8–1.8 V. The 6-switch converter includes a 3X-step-down switched capacitor (SC) front-end that is fully soft-charged and shared by three output inductors. The output voltages are individually regulated using PWM signals from a power-collaborative control (PCC). The chip was manufactured in a 130-nm high-voltage BCD process, achieving a peak efficiency of 87.14%, 30X conversion ratio, and 11.93-W peak output power in system evaluation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"3-14"},"PeriodicalIF":3.2,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11300850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 75-pJ/bit 435-MHz 16-QAM Modulator With 20-ns Startup Time and Symbol-Level Duty Cycling for Capsule Endoscopy","authors":"Donghyun Youn;Daehyeon Kwon;Minkyu Je","doi":"10.1109/OJSSCS.2025.3644839","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3644839","url":null,"abstract":"Wireless capsule endoscopy requires simultaneous support of ultralow-power operation and high data rate to enable long diagnostic time and reliable image transmission. To support both design requirements, this work presents a 75-pJ/bit 435-MHz modulator for 16 quadrature amplitude modulation (16-QAM) with aggressive symbol-level duty cycling (SLDC). An SLDC is supported by a fast startup technique, which enhances duty cycling efficiency. During startup, the proposed technique minimizes transient DC error components at the modulator input, which results in fast settling of the output envelope. A fully on-chip auto calibration detects and corrects this error without impacting modulator performance. The calibration is fully digital, scalable, and robust against process, voltage, and temperature variations. After the calibration process, the modulator exhibits a 20-ns startup time. Even with 50% SLDC, a data rate of 20 Mb/s is achieved with −8-dBm average output power and 1.6-mW power consumption. Combining spectrum-efficient QAM and SLDC, this work satisfies both low-power and high-data-rate requirements for wireless medical capsule endoscopy (WMCE).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"354-364"},"PeriodicalIF":3.2,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11300849","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}