IEEE Open Journal of the Solid-State Circuits Society最新文献

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Low-Power Heterodyne Receiver Architectures: Review, Theory, and Examples 低功耗外差接收器架构:回顾、理论和示例
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-10-10 DOI: 10.1109/OJSSCS.2023.3322671
Aman Gupta;Trevor J. Odelberg;David D. Wentzloff
{"title":"Low-Power Heterodyne Receiver Architectures: Review, Theory, and Examples","authors":"Aman Gupta;Trevor J. Odelberg;David D. Wentzloff","doi":"10.1109/OJSSCS.2023.3322671","DOIUrl":"10.1109/OJSSCS.2023.3322671","url":null,"abstract":"The growth of the Internet of Things (IoT) has led to a massive upsurge in low-power radio research. Specifically, low-power receivers (RX) have been developed that efficiently receive data and extend the battery life for energy-constrained IoT systems. This has led to innovations in energy-detector (ED) first RXs which can achieve much lower power than traditional mixer-based heterodyne architectures. However, at such low-power levels, the RX performance is extremely limited. Oftentimes, low-power RXs have severe performance limitations, including lower data rate, limited blocker rejection, lower sensitivity, lower tolerance to PVT, limited modulation compatibility, and increased size and cost of off-chip components to achieve passive gain. This greatly limits the application of such RXs in real-world applications and prevents many of the low-power circuit techniques from translating to commercial standards. In this work, we look to motivate research into low-power heterodyne RX architectures which can support higher order modulation and have improved RX specifications while retaining low power.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"225-238"},"PeriodicalIF":0.0,"publicationDate":"2023-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10275080","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136208330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Power Circuit Interfaces for Strain Modulated Multiferroic Biomagnetic Sensors 应变调制多铁磁传感器的低功耗电路接口
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-10-05 DOI: 10.1109/OJSSCS.2023.3321008
Yujia Huo;Sydney Sofronici;Michael J. D’Agati;Roy H. Olsson
{"title":"Low Power Circuit Interfaces for Strain Modulated Multiferroic Biomagnetic Sensors","authors":"Yujia Huo;Sydney Sofronici;Michael J. D’Agati;Roy H. Olsson","doi":"10.1109/OJSSCS.2023.3321008","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3321008","url":null,"abstract":"The recording and analysis of biomagnetic fields have widespread applications in medical research and diagnostics. Wearable magnetic field sensors offer a noncontact and portable method for sensing biopotentials. This article presents a readout circuit in 180-nm CMOS for strain-modulated multiferroic vector magnetic field sensors. By utilizing a demodulator-first architecture, the circuit bandwidth and dynamic range requirements are greatly reduced allowing for a low power consumption of 5.9 mW. The circuit bandwidth is from 76 mHz to 2.2 kHz, allowing for measurement across the range of interest for biomagnetic signals. Utilizing a modulation noise cancellation technique, the noise performance of the sensor system is significantly improved, and the sensor modulation amplitude can be increased, resulting in improved sensor sensitivity. Measurements for the sensor-readout system demonstrate a 144 pT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz magnetic noise floor at 1 kHz. The noise and power consumption are significantly lower than alternative magnetic sensor systems of similar volume.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"214-222"},"PeriodicalIF":0.0,"publicationDate":"2023-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10272978","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134795091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers 用于汽车接收机的高速和高性能连续时间adc
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-29 DOI: 10.1109/OJSSCS.2023.3317817
Lucien J. Breems;Muhammed Bolatkale;Qilong Liu;Pierluigi Cenci
{"title":"High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers","authors":"Lucien J. Breems;Muhammed Bolatkale;Qilong Liu;Pierluigi Cenci","doi":"10.1109/OJSSCS.2023.3317817","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3317817","url":null,"abstract":"This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"174-184"},"PeriodicalIF":0.0,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10268251","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134794993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Recent Trends and Challenges in Near-Field Wireless Power Transfer Systems 近场无线电力传输系统的最新趋势和挑战
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-11 DOI: 10.1109/OJSSCS.2023.3313575
Elisabetta Moisello;Alessandro Liotta;Piero Malcovati;Edoardo Bonizzoni
{"title":"Recent Trends and Challenges in Near-Field Wireless Power Transfer Systems","authors":"Elisabetta Moisello;Alessandro Liotta;Piero Malcovati;Edoardo Bonizzoni","doi":"10.1109/OJSSCS.2023.3313575","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3313575","url":null,"abstract":"In recent years, wireless power transfer (WPT) has become a widespread method for charging and powering devices, including but not limited to consumer electronics, industrial applications, electric vehicles, medical devices, and sensor nodes. This article provides an overview of the available WPT technologies, focusing on the near-field case, and highlights the main architecture and circuit-level challenges encountered in the implementation of magnetic-based near-field WPT systems while reviewing the proposed solutions in the literature, in order to identify the main research interests as well as the trends for the future.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"197-213"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10246316","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134795090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion 连续时间流水线ADC:一种用于宽带数据转换的连续时间ADC
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-11 DOI: 10.1109/OJSSCS.2023.3313579
Hajime Shibata
{"title":"Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion","authors":"Hajime Shibata","doi":"10.1109/OJSSCS.2023.3313579","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3313579","url":null,"abstract":"The continuous-time (CT) pipelined analog-to-digital converter (ADC) is an emerging ADC architecture suitable for wide- bandwidth (BW) digitization in fully integrated receiver applications. It inherits the integration-friendly features of CT \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 ADCs, such as inherent anti-aliasing, while achieving the wide- BW operation originating from discrete-time (DT) pipelined ADCs. In this review article, we introduce a gain-centric ADC model and apply the key criteria derived from the model to transform a DT pipelined ADC into a CT pipelined ADC. We then discuss the design considerations and essential building blocks of the CT pipelined ADC. Finally, we examine several implementations of this architecture with their highlights and challenges.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"162-173"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10246305.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A WiFi and Bluetooth Low-Energy Backscatter Combo Chip With Beam Steering Capabilities 具有光束转向功能的 WiFi 和蓝牙低功耗反向散射组合芯片
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-11 DOI: 10.1109/OJSSCS.2023.3308530
Shih-Kai Kuo;Manideep Dunna;Dinesh Bharadia;Patrick P. Mercier
{"title":"A WiFi and Bluetooth Low-Energy Backscatter Combo Chip With Beam Steering Capabilities","authors":"Shih-Kai Kuo;Manideep Dunna;Dinesh Bharadia;Patrick P. Mercier","doi":"10.1109/OJSSCS.2023.3308530","DOIUrl":"10.1109/OJSSCS.2023.3308530","url":null,"abstract":"This article introduces a dual-mode backscatter integrated circuit that supports both WiFi and Bluetooth low-energy (BLE) transmissions. It enables a multiantenna WiFi mode with reconfigurable beam steering of single-sideband (SSB) quadrature phase shift-keying (QPSK) signals, while also facilitating omnidirectional SSB BLE-to-BLE backscatter communication. To achieve beam steering, two techniques are proposed: 1) a transmission-line-less fully reflective SP4T backscatter switch is employed to minimize power loss and maximize the communication range and 2) a multiantenna array is constructed using the aforementioned SP4T switches together with a baseband phase-shifting technique to reradiate the incident WiFi signal with a controllable angle of direction. The chip implementation is based on a 65-nm CMOS process and operates at a power consumption of \u0000<inline-formula> <tex-math>$5.5 mu text{W}$ </tex-math></inline-formula>\u0000 in standby mode. In backscattering mode, it consumes \u0000<inline-formula> <tex-math>$39 mu text{W}$ </tex-math></inline-formula>\u0000 for the single-antenna approach and \u0000<inline-formula> <tex-math>$88 mu text{W}$ </tex-math></inline-formula>\u0000 for the multiantenna approach. The proposed design achieves a worst-case access point (AP)-to-AP range of 35 and 56 m for the single-antenna and multiantenna approaches, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"239-248"},"PeriodicalIF":0.0,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10246802","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135361278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Techniques for Energy-Efficient Analog-to-Digital Converters 节能模数转换器的设计技术
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-08 DOI: 10.1109/OJSSCS.2023.3311418
Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae
{"title":"Design Techniques for Energy-Efficient Analog-to-Digital Converters","authors":"Moonhyung Jang;Xiyuan Tang;Yong Lim;John G. Kauffman;Nan Sun;Maurits Ortmanns;Youngcheol Chae","doi":"10.1109/OJSSCS.2023.3311418","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3311418","url":null,"abstract":"The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"145-161"},"PeriodicalIF":0.0,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10246164.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks 基于对称压缩三权神经网络的3.8 μ w 10关键字噪声鲁棒关键字识别处理器
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-09-06 DOI: 10.1109/OJSSCS.2023.3312354
Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai
{"title":"A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks","authors":"Bo Liu;Na Xie;Renyuan Zhang;Haichuan Yang;Ziyu Wang;Deliang Fan;Zhen Wang;Weiqiang Liu;Hao Cai","doi":"10.1109/OJSSCS.2023.3312354","DOIUrl":"10.1109/OJSSCS.2023.3312354","url":null,"abstract":"A ternary-weight neural network (TWN) inspired keyword spotting (KWS) processor is proposed to support complicated and variable application scenarios. To achieve high-precision recognition of ten keywords under 5 dB~Clean wide range of background noises, a convolution neural network consists of four convolution layers and four fully connected layers, with modified sparsity-controllable truncated Gaussian approximation-based ternary-weight training is used. End-to-end optimization composed of three techniques is utilized: 1) the stage-by-stage bit-width selection algorithm to optimize the hardware overhead of FFT; 2) the lossy compressed TWN with symmetric kernel training (SKT) and dedicated internal data reuse computation flow; and 3) the error intercompensation approximate addition tree to reduce the computation overhead with marginal accuracy loss. Fabricated in an industrial 22-nm CMOS process, the processor realizes up to ten keywords in real-time recognition under 11 background noise types, with the accuracy of 90.6%@clean and 85.4%@5 dB. It consumes an average power of \u0000<inline-formula> <tex-math>$3.8 ~mu text{W}$ </tex-math></inline-formula>\u0000 at 250 kHz and the normalized energy efficiency is \u0000<inline-formula> <tex-math>$2.79times $ </tex-math></inline-formula>\u0000 higher than state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"185-196"},"PeriodicalIF":0.0,"publicationDate":"2023-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10242041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79901424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network 具有内置AM–PM补偿和单变压器输出网络的数字功率放大器
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-08-11 DOI: 10.1109/OJSSCS.2023.3304599
Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang
{"title":"A Digital Power Amplifier With Built-In AM–PM Compensation and a Single-Transformer Output Network","authors":"Jeongseok Lee;Doohwan Jung;David Munzer;Hua Wang","doi":"10.1109/OJSSCS.2023.3304599","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3304599","url":null,"abstract":"This article presents a digital power amplifier (DPA) with a built-in AM–PM compensation technique and a compact single-transformer footprint. The AM–PM distortion behavior of the current-mode/voltage-mode power amplifiers (PAs) is detailed and an AM–PM compensation technique for both modes is introduced. The proposed design utilizes one current-mode DPA as the main path PA and a class-G PA voltage-mode digital PA as the auxiliary path PA, combined through a single-transformer footprint. It provides enhanced linearity through built-in adaptive biasing and hybrid current-/voltage-mode Doherty-based power combining. As a proof of concept, a 1.2–2.4-GHz wideband DPA is implemented in the Globalfoundries 45-nm CMOS SOI process. The measurements show a 37.6% peak drain efficiency (DE) at 1.4 GHz, and 21.8-dBm saturated output power (Psat) and \u0000<inline-formula> <tex-math>$1.2times /1.4times $ </tex-math></inline-formula>\u0000 power back-off (PBO) efficiency enhancement, compared to the ideal class-B at 3 dB/6 dB PBO at 1.2 GHz. This proposed digital PA supports 20-MSym/s 64-QAM modulation at 14.8-dBm average output power and 22.8% average PA DE while maintaining error vector magnitude (EVM) lower than −23 dB without any phase predistortion. To the best of our knowledge, this is the first demonstration of hybrid current–voltage-mode Doherty power combining on a single-footprint transformer over a broad bandwidth (BW).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"134-144"},"PeriodicalIF":0.0,"publicationDate":"2023-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10214532.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Open Journal of Solid-State Circuits Society Special Section on Biomedical Electronics IEEE固态电路学会开放期刊生物医学电子学专刊
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-07-06 DOI: 10.1109/OJSSCS.2023.3281904
Jerald Yoo
{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on Biomedical Electronics","authors":"Jerald Yoo","doi":"10.1109/OJSSCS.2023.3281904","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3281904","url":null,"abstract":"Recent advances in biomedical electronics have opened the doors to pervasive/wearable technologies as well as bioinspired systems. Traditional disease treatment is shifting toward preemptive, personalized healthcare. For these biomedical electronics to work seamlessly, careful design of integrated circuits for sensing, signal processing, and powering is crucial. However, biomedical applications often are under unique and harsh environments, such as under extremely stringent power budgets and fluctuating supply voltages; on top of this, such applications require hermetic sealing with robust communications. Moreover, we also need to consider various aspects that other applications do not normally consider. As an example, the human body absorbs GHz range electromagnetic signals significantly, making typical RF communication and powering technologies such as Bluetooth or wireless power transfer (WPT) in GHz not an ideal choice in/around body area [1]. Also, with the rise of artificial intelligence and machine learning, personalized healthcare is becoming more popular, but for some applications, “personalized” means that training sets may get scarce, posing issues to achieving high sensitivity and specificity at once. This special Section will present the latest developments in integrated circuits in biomedical electronics to overcome the aforementioned issues: powering, sensing, and processing.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"63-64"},"PeriodicalIF":0.0,"publicationDate":"2023-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10174830.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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