IEEE Open Journal of the Solid-State Circuits Society最新文献

{"title":"Recent Advances in Energy-Efficient and Temperature-Resilient Sensor Interfaces","authors":"Woojun Choi;Inhee Lee;Youngwoo Ji;Alexander Delke;Sining Pan;Zhong Tang;Youngcheol Chae","doi":"10.1109/OJSSCS.2025.3634970","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3634970","url":null,"abstract":"The rapid growth of power-constrained applications, including the Internet of Things (IoT) and wearables, demands sensor interfaces with high accuracy and reliability. A fundamental design challenge arises as their performance is severely limited by thermal drift within the analog front-end (AFE) and analog-to-digital converter (ADC) circuits. To address this, this article reviews two principal strategies: 1) the development of robust voltage and frequency reference circuits and 2) the implementation of on-chip temperature calibration. The review covers state-of-the-art temperature-compensated voltage references, such as subthreshold and BJT/MOS hybrid architectures, as well as stable frequency references based on LC and RC time constants. Furthermore, it examines advanced sensor interfaces that integrate on-chip temperature sensors for real-time error correction, featuring recent case studies on current sensor designs. These comprehensive advances are crucial for enabling reliable, energy-efficient sensor interfaces intended for precision-critical applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"456-469"},"PeriodicalIF":3.2,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11260455","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A PVT-Tolerant, Curvature-Compensated CMOS Bandgap-Based Current Reference With Single-Point Batch Trim","authors":"Ayman Sakr;Mohamed Atef Hassan;Jens Anders","doi":"10.1109/OJSSCS.2025.3633660","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3633660","url":null,"abstract":"Traditional bandgap-based current references display various limitations. This includes large temperature coefficients (TCs) across process corners, necessitating costly trimming cycles, and area inefficiency for low current values (<<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>A). This work addresses these shortcomings by generating a complementary-to-absolute-temperature (CTAT) current that reproduces the temperature dependence of the proportional-to-absolute-temperature (PTAT) current, including its curvature over process corners, eliminating multitemperature TC trimming while retaining a single-point room-temperature calibration to set the absolute current. The design provides this matching PTAT/CTAT feature by relying on the temperature-stable negative TC of the electron mobility to generate the CTAT current instead of the nonlinear and process-sensitive diode-based CTAT generation. Moreover, thanks to the mobility-based CTAT generation, high-resistivity undoped poly resistors with a strong negative TC can be used, enabling area-efficient CTAT current generation in the sub-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A to single-digit <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A range. To validate the proposed approach, we fabricated a prototype design in a 130-nm SOI CMOS technology, occupying an active area of only 0.016 mm2 and operating over a wide supply range from 1.6 to 3 V. Measurements from 10 chips yield a mean current of <inline-formula> <tex-math>$1.1~mu $ </tex-math></inline-formula>A (<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>/<inline-formula> <tex-math>$mu ~approx ~4.4$ </tex-math></inline-formula>%) close to the design target of <inline-formula> <tex-math>$1.2~mu $ </tex-math></inline-formula>A. Experimental results further demonstrate an average TC of 110 ppm/°C from <inline-formula> <tex-math>$0~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$100~^{circ }$ </tex-math></inline-formula>C without multitemperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"470-480"},"PeriodicalIF":3.2,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11251149","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Current-Steering 6-GHz Power Amplifier With Extensive Reconfigurability for Cryogenic Operation in 65 nm CMOS","authors":"Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3631573","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3631573","url":null,"abstract":"Emerging W<sc>ireless</small> sensor networks for deep space exploration demand highly reliable RF transmitters capable of operating in extreme environments, where temperatures can drop well below liquid nitrogen temperature. CMOS power amplifiers (PAs) for these systems must withstand wide temperature variations and preserve output power and linearity despite significant cryogenic shifts in MOSFET parameters such as threshold voltage and carrier mobility. Conventional process design kit (PDK) models, limited to–55 °C to 125 °C, exacerbate the challenge by offering insufficient support for cryogenic design and validation. This work introduces a high-efficiency current-steering CMOS PA designed for robust operation at cryogenic temperatures down to 4.2 K. The PA employs a reconfigurable output stage to compensate for temperature-induced device variations and uses current-steering device pairs to shape drain current at the output stage for enhancing efficiency and linearity. A 65-nm CMOS prototype achieves a peak drain efficiency (DE) of 42.8% and an OP1dB of 13.6 dBm at 6.3 GHz when cooled to 4.2 K. These results highlight the potential of highly configurable CMOS PAs for enabling energy-efficient wireless communication in space and other extreme cryogenic environments.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"497-510"},"PeriodicalIF":3.2,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11240125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 64-Element 28 GHz Digital Beamformer Based on Tileable Synchronized Distributed Beamforming Chiplets","authors":"Christine Weston;Rundao Lu;Zhengqi Xu;Hao Yu;Daniel Lambalot;Michael P. Flynn","doi":"10.1109/OJSSCS.2025.3625891","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3625891","url":null,"abstract":"A tileable 16-element, 4-beam, 28 GHz digital beamforming chiplet communicates over a power-efficient, low-latency Streaming-Advanced Interface Bus (AIB) data link to distribute digital beamforming processing across multiple chiplets. Spiral chiplet connectivity enables scaling to a large array size with a single beamforming chiplet design. The chiplet includes a 28 GHz frontend, analog-to-digital converters (ADCs), digital beamform processing and Streaming-AIB receive and transmit interfaces. A multichip digital phase-locked loop (PLL) ensures digital clock synchronization between chiplets. Scalability is demonstrated with a prototype 4-chiplet, 64-element module. Over-the-air tests confirm accurate 64-element beam patterns, a double-sideband (DSB) noise figure of 17 dB, a Streaming-AIB bit error rate (BER) of 3E-12, and a low power consumption of 23 mW per beam-channel.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"424-436"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dynamically Reconfigurable Power Management System With Self-Monitoring Capabilities for Energy-Efficient SoCs","authors":"Henrique Pocinho;Rodrigo Capeleiro;Tiago Moita;José Proença;Floriberto Lima;Marcelino B. Dos Santos;Fábio Passos","doi":"10.1109/OJSSCS.2025.3624690","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3624690","url":null,"abstract":"This article presents a dynamically reconfigurable power management unit (PMU) with self-monitoring capabilities, designed to enable ultralow power (ULP) operation. The proposed system consumes just <inline-formula> <tex-math>$1.68~{mu }$ </tex-math></inline-formula>W, which represents a 30% reduction in power consumption when compared to state-of-the-art implementations operating at 32 kHz. Fabricated in 22-nm FD-SOI technology, the proposed PMU leverages a novel real-time clock (RTC) architecture that provides performance and workload self-monitoring capabilities and also has the capability to change its operation modes automatically based on current workload. With the usage of such RTC, the PMU eliminates the need for external control units, complex state machines or processors, significantly reducing system complexity and silicon area. Since RTCs are already present in many systems and the proposed architecture only requires a 15% area increase for additional state-control registers, it makes it particularly well-suited for implantable, wearable or other Internet of Medical Things (IoMT) devices, where energy autonomy, system miniaturization, and safe long-term operation are essential.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"365-376"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218198","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems","authors":"Lukas Pfromm;Alish Kanani;Harsh Sharma;Janardhan Rao Doppa;Partha Pratim Pande;Umit Y. Ogras","doi":"10.1109/OJSSCS.2025.3626314","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3626314","url":null,"abstract":"Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework’s versatility, up to 340% accuracy improvement, and power/thermal analysis capability.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"410-423"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218851","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LO Generation Techniques for Millimeter-Wave Receivers","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2025.3622592","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3622592","url":null,"abstract":"Millimeter-wave radios hold promise for supporting high data rates in wireless communication. A key challenge in the development of these radios relates to the generation of the local oscillator (LO) waveform(s) necessary for upconversion and downconversion. This article presents a number of such techniques in the context of four receivers operating at 28, 140, and 300 GHz. The proposed concepts focus on fundamental-mode LO synthesis and high-speed inductorless frequency dividers. New methods of LO phase shifting for beamforming applications are also introduced. The prototypes have been fabricated in 28-nm CMOS technology and exhibit rms jitter values ranging from 106 fs to 640 fs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"310-321"},"PeriodicalIF":3.2,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11206376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on RF Circuits and Wireless Transceivers","authors":"Wei Deng;Minyoung Song;Aarno Pärssinen","doi":"10.1109/OJSSCS.2025.3616271","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3616271","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"269-270"},"PeriodicalIF":3.2,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202698","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel-Scale Reconfigurable Photonic Interconnects for Scalable AI Computation","authors":"Tzu-Chien Hsueh;Bill Lin;Zijun Chen;Yeshaiahu Fainman","doi":"10.1109/OJSSCS.2025.3620371","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3620371","url":null,"abstract":"Panel-scale reconfigurable photonic interconnects on a glass substrate up to 500-mm <inline-formula> <tex-math>$times 500$ </tex-math></inline-formula>-mm or larger are envisioned by proposing a novel photonic switch fabric that enables all directional panel-edge-to-panel-edge reach without active repeaters while offering high communication bandwidth, planar-direction reconfigurability, low energy consumption, and compelling data bandwidth density for heterogeneous integration of an in-package artificial intelligence computing system on a photonic interposer exceeding thousands of centimeters square. The proposed approach focuses on reconfigurable photonic interconnects, which are integration-compatible with commercial processor chiplets and 3-D high-bandwidth memory stacks, to create a novel panel-scale heterogeneously integrated package enabled by high-capacity wavelength-division-multiplexing optical data links using advanced optical modulators, broadband photodetector, novel optical crossbar switches with multilayer waveguides, and on-chip frequency comb sources.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"437-453"},"PeriodicalIF":3.2,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11201050","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Toward Power and EMSCA Resilience","authors":"Archisman Ghosh;Md. Abdur Rahman;Debayan Das;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3610567","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3610567","url":null,"abstract":"Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc.) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at the <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula> port. Although any digital implementation has two generic ports, namely, clock and <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>, circuit-level countermeasures primarily focus on the <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula> port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew, making it difficult for side-channel analysis. Due to this, minimum traces-to-disclosure (MTD) improves by <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect (<inline-formula> <tex-math>$1800times $ </tex-math></inline-formula>) more than the multiplication of individual techniques (<inline-formula> <tex-math>$100times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$5times $ </tex-math></inline-formula>, respectively) at the cost of 11% area overhead, <3% power overhead (measured), and <6% performance overhead (measured).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"295-309"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}