IEEE Open Journal of the Solid-State Circuits Society最新文献

{"title":"Analog Front-End Circuit Techniques for Wearable ExG, BioZ, and PPG Signal Acquisition: A Review","authors":"Jiawei Xu;Tianxiang Qu;Qinjing Pan;Yijie Li;Liheng Liu;Yuying Li;Jianhong Zhou;Chang Yao;Zhiliang Hong","doi":"10.1109/OJSSCS.2025.3610583","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3610583","url":null,"abstract":"Wearable platforms that concurrently acquire multiple physiological signals enable comprehensive health monitoring but impose stringent requirements on front-end circuit design. The reliable extraction of low-amplitude and low-frequency biosignals is hindered by electrode offset, noise, motion artifacts, and environmental interference. Recent efforts have advanced analog front ends (AFEs) for biopotential (ExG), bioimpedance (BioZ), and photoplethysmography (PPG) sensing, with emphasis on optimizing key metrics such as noise efficiency, input impedance, dynamic range, CMRR, and power consumption. In addition, digitally-assisted calibration and direct-digitization schemes have emerged as alternative design directions, offering enhanced robustness and scalability while introducing tradeoffs in complexity and energy efficiency. This review surveys these circuit techniques, analyzes their design tradeoffs, and outlines future opportunities for next-generation wearable biomedical interfaces.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"251-268"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165115","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.45-mm² 3.49-TOPS/W Cryogenic Deep Reinforcement Learning Module for End-to-End Integrated Circuits Control","authors":"Jiachen Xu;John Kan;Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3601153","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3601153","url":null,"abstract":"This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-<inline-formula> <tex-math>${mathrm { mm}}^{2}$ </tex-math></inline-formula> core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of <inline-formula> <tex-math>$4.925~mu $ </tex-math></inline-formula>s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K (<inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C) to 4.2 K (–<inline-formula> <tex-math>$269~^{circ }$ </tex-math></inline-formula>C).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"240-250"},"PeriodicalIF":3.2,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11133470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast-Locking and High-Resolution DLL With Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS","authors":"Nicolás Wainstein;Eran Avitay;Eugene Avner","doi":"10.1109/OJSSCS.2025.3597909","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3597909","url":null,"abstract":"This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog converter (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the BS controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75-V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed design achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking and resolution FoM of 0.01 pJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>ns2.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"229-239"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11122556","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Data Converters","authors":"Youngcheol Chae;Mike Shuo-Wei Chen","doi":"10.1109/OJSSCS.2025.3561812","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3561812","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"144-144"},"PeriodicalIF":0.0,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11039224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Overview of AI Hardware Architectures and Silicon for 3-D Spatial Computing Systems","authors":"Dongseok Im;Gwangtae Park;Junha Ryu;Hoi-Jun Yoo","doi":"10.1109/OJSSCS.2025.3577110","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3577110","url":null,"abstract":"As artificial intelligence (AI) advances, 3-D spatial computing has emerged as a key application in various fields. It interprets the 3-D space surrounding users and provides them with useful information. This article presents a survey of AI hardware architectures and silicon solutions for 3-D spatial computing systems. The survey categorizes five domains: 1) 3-D data capturing; 2) 3-D data analysis; 3) 3-D hand motion analysis; 4) simultaneous localization and mapping (SLAM); and 5) 3-D rendering. Each session analyzes design considerations for domain-specific accelerators. Finally, this article discusses a next-generation 3-D spatial computing platform that integrates various functions of 3-D spatial computing systems using AI technologies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"212-228"},"PeriodicalIF":0.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11026096","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2025.3534449","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3534449","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143848774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LTPO-TFT-Based Pixel Circuit With TFT, OLED, and Supply Voltage Compensation for Enhanced Luminance Uniformity in Variable-Frame-Rate AMOLED Smartwatch Displays","authors":"Jui-Hung Chang;Cheng-Han Ke;Chia-Lun Lee;Po-Cheng Lai;Chi-Hsuan Huang;Li-Wei Shih;Chih-Lung Lin","doi":"10.1109/OJSSCS.2025.3560242","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3560242","url":null,"abstract":"This work proposes a new pixel circuit using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs) for use in variable-frame-rate active-matrix organic light-emitting diode (AMOLED) smartwatch displays. The proposed circuit, including seven TFTs and two capacitors, can compensate for threshold voltage (<inline-formula> <tex-math>$V_{mathrm { TH}}$ </tex-math></inline-formula>) variations of the driving TFTs (DTFTs), the turn-on voltages of the OLEDs (<inline-formula> <tex-math>$V_{mathrm { OLED}}$ </tex-math></inline-formula>), and <inline-formula> <tex-math>$V_{mathrm { SS}}$ </tex-math></inline-formula> IR rises; it is immune to <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> IR drops. It employs amorphous-indium-gallium-zinc-oxide (a-IGZO) TFTs, which exhibit low leakage currents, suppressing distortion in the gate voltage of the DTFT at low frame rates and enabling a stable OLED current (<inline-formula> <tex-math>$I_{mathrm { OLED}}$ </tex-math></inline-formula>) to maintain consistent display luminance. A 1.28-In LTPO AMOLED panel with a <inline-formula> <tex-math>$416times 416$ </tex-math></inline-formula> resolution and the proposed pixel circuit are fabricated to verify the circuit’s performance. The experimental results thus obtained confirm that red, green, blue, and white images at frame rates from 45 to 1 Hz exhibit uniformity without visible spot or line defects and a luminance error rate below 2.34%. Measured luminance values remain stable at gray levels of 32, 64, 128, and 255 during an extended emission period of 1 s, revealing no perceived image flicker at 1 Hz (with a Japan Electronics and Information Technology Industries Association flicker value below −54.747 dB). Therefore, the proposed circuit, with its highly uniform and stable currents at various frame rates, is promising for use in AMOLED smartwatch displays.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"130-143"},"PeriodicalIF":0.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963900","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143925088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout","authors":"Rui Xu;Jaroslav Bán;Sarthak Kalani;Chen-Kai Hsu;Subhajit Ray;Brian Kirby;Gabriel Matos;Julia Gonski;Andrew C. Smith;Daniel M. Williams;Kiley E. Kennedy;Alan Kahn;Michelle Contreras-Cossio;Lauren Larson;Michael Himmelsbach;Devanshu Panchal;Michael Unanian;Xiangxing Yang;Nan Sun;John Parsons;Timothy R. Andeen;Peter R. Kinget","doi":"10.1109/OJSSCS.2025.3573904","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3573904","url":null,"abstract":"The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"180-199"},"PeriodicalIF":0.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017335","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dual-SSHC Rectifier With Digital-DCB MPPT for Triboelectric Energy Harvesting","authors":"Wenyu Peng;Xinling Yue;Willem D. van Driel;Guoqi Zhang;Sijun Du","doi":"10.1109/OJSSCS.2025.3573905","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3573905","url":null,"abstract":"Triboelectric nanogenerator (TENG), advantageous in high energy density and flexibility, is promising as a sustainable energy source but can hardly be used to power edge devices directly due to its high-voltage ac output and varying capacitive impedance. To address it, this work proposes a power-conditioning interface with a fully integrated dual synchronous switch harvesting on capacitors (D-SSHC) rectifier for triboelectric energy extraction. Furthermore, a full digital duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm is developed to optimize the energy harvesting efficiency with simple implementation and continuous tracking. Designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process, the proposed interface can extract energy at a maximum output voltage of 70 V. According to the measurement results, it achieves 99% MPPT efficiency and an energy extraction improvement of 598% compared to a full-bridge rectifier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"200-211"},"PeriodicalIF":0.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11016074","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New Associate Editors","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3540393","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3540393","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"101-103"},"PeriodicalIF":0.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10936518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}