IEEE Open Journal of the Solid-State Circuits Society最新文献

New Associate Editors

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-03-21 DOI: 10.1109/OJSSCS.2025.3540393

Woogeun Rhee

引用次数: 0

2024 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 4

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-02-25 DOI: 10.1109/OJSSCS.2025.3545275

引用次数: 0

Editorial Message From the Incoming Editor-in-Chief

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-02-20 DOI: 10.1109/OJSSCS.2025.3526922

Woogeun Rhee

引用次数: 0

Editorial Special section on High-Performance Wireline Transceiver Circuits

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-02-19 DOI: 10.1109/OJSSCS.2025.3526924

Sam Palermo;Jaeduk Han

引用次数: 0

Wideband Continuous-Time MASH ADCs: Principles, Challenges, and Prospects

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-02-19 DOI: 10.1109/OJSSCS.2025.3543761

Ke Li;Liang Qi;Mingqiang Guo;Rui P. Martins;Sai-Weng Sin

引用次数: 0

Editorial Special Section on High-Performance Frequency Synthesizers

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-02-07 DOI: 10.1109/OJSSCS.2025.3526923

Salvatore Levantino;Wanghua Wu

引用次数: 0

SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-01-13 DOI: 10.1109/OJSSCS.2024.3524495

Rajiv V. Joshi;J. Frougier;Alberto Cestero;Crystal Castellanos;Sudipto Chakraborty;Carl Radens;M. Silvestre;S. Lucarini;I. Ahsan;E. Leobandung

{"title":"SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology","authors":"Rajiv V. Joshi;J. Frougier;Alberto Cestero;Crystal Castellanos;Sudipto Chakraborty;Carl Radens;M. Silvestre;S. Lucarini;I. Ahsan;E. Leobandung","doi":"10.1109/OJSSCS.2024.3524495","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3524495","url":null,"abstract":"A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—<inline-formula> <tex-math>$0.026~mu $ </tex-math></inline-formula>m<sup>2</sup>, and high current—<inline-formula> <tex-math>$0.032~mu $ </tex-math></inline-formula>m<sup>2</sup>).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"60-74"},"PeriodicalIF":0.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839490","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143388591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-01-06 DOI: 10.1109/OJSSCS.2025.3526132

Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue

{"title":"Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers","authors":"Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue","doi":"10.1109/OJSSCS.2025.3526132","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526132","url":null,"abstract":"The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"86-100"},"PeriodicalIF":0.0,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10824885","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

How to Design a Differential CMOS LC Oscillator

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-31 DOI: 10.1109/OJSSCS.2024.3524493

Asad A. Abidi;David Murphy

引用次数: 0

A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-26 DOI: 10.1109/OJSSCS.2024.3523245

Sumukh Prashant Bhanushali;Arindam Sanyal

引用次数: 0