IEEE Open Journal of the Solid-State Circuits Society最新文献

The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation 5G FR2 相控阵中的杂散发射问题，以及基于嵌入式 LO 漏泄消除的上混频器的解决方案

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-10-28 DOI: 10.1109/OJSSCS.2024.3487548

Arun Paidimarri;Yujiro Tojo;Caglar Ozdag;Alberto Valdes-Garcia;Bodhisatwa Sadhu

{"title":"The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation","authors":"Arun Paidimarri;Yujiro Tojo;Caglar Ozdag;Alberto Valdes-Garcia;Bodhisatwa Sadhu","doi":"10.1109/OJSSCS.2024.3487548","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3487548","url":null,"abstract":"The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this article, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meet these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the upmixer. We introduce two actuator circuits to control two independent LO signals at the upmixer output, one resulting from the upconversion from dc to LO, and another resulting from downconversion from 2 LO to LO. These two independent LO outputs then provide 2-D phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the upmixer. The LO cancellation results in better than −57-dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a 60 beam steering range.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"193-211"},"PeriodicalIF":0.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10737135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142679264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SAR-Assisted Energy-Efficient Hybrid ADCs SAR 辅助型高能效混合 ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-10-01 DOI: 10.1109/OJSSCS.2024.3472000

Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu

引用次数: 0

Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth 基于系统方程设计具有 2 GHz 分辨率带宽的 10 位 500-MS/s 单通道 SAR A/D 转换器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-26 DOI: 10.1109/OJSSCS.2024.3469109

Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi

引用次数: 0

Digital Phase-Locked Loops: Exploring Different Boundaries 数字锁相环：探索不同的边界

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-20 DOI: 10.1109/OJSSCS.2024.3464551

Yuncheng Zhang;Dingxin Xu;Kenichi Okada

{"title":"Digital Phase-Locked Loops: Exploring Different Boundaries","authors":"Yuncheng Zhang;Dingxin Xu;Kenichi Okada","doi":"10.1109/OJSSCS.2024.3464551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3464551","url":null,"abstract":"This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"176-192"},"PeriodicalIF":0.0,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10684740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142524125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox 8 型电感器：射频集成电路设计人员工具箱中的重要补充

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-06 DOI: 10.1109/OJSSCS.2024.3455269

Pingda Guan;Haikun Jia;Wei Deng;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi

引用次数: 0

Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at K/Ka- and E/W-Band 在 K/Ka 和 E/W 波段使用晶格网络的超宽带 4 位分布式移相器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-02 DOI: 10.1109/OJSSCS.2024.3453777

Sungwon Kwon;Minjae Jung;Byung-Wook Min

{"title":"Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at K/Ka- and E/W-Band","authors":"Sungwon Kwon;Minjae Jung;Byung-Wook Min","doi":"10.1109/OJSSCS.2024.3453777","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3453777","url":null,"abstract":"In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.6pm 0$ </tex-math></inline-formula>\u0000.8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.9pm 1$ </tex-math></inline-formula>\u0000.1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"122-130"},"PeriodicalIF":0.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations 增强功率放大器中的射频指纹生成：不等间隔多音设计方法和注意事项

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-08-30 DOI: 10.1109/OJSSCS.2024.3451401

Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen

{"title":"Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations","authors":"Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2024.3451401","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3451401","url":null,"abstract":"The rapid growth of Internet of Things (IoT) devices and communication standards has led to an increasing demand for data security, particularly with limited hardware resources. In addition to conventional software-level data encryption, physical-layer security techniques, such as device-specific radio frequency fingerprints (RFFs), are emerging as promising solutions. This article first summarizes prior arts on timestamped RFFs generation and reconfigurable power amplifier (PA) designs. Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. Multiple 3-bit resistive digital-to-analog converters (RDACs) are applied to control body biasing units within the two-stage PA, facilitating the generation of massive and distinguishable RFFs. Subsequently, time-varying unequally spaced multitone (USMT) techniques are proposed to further elevate the count of available timestamped RFFs from 4096 to 16 384. The validation results of RFFs utilizing 64-QAM WiFi-6E advertising packets, employing time-varying USMT transmitted within the 5.39–5.41-GHz band, confirm the successful generation of 16 384 distinct RFF patterns. Moreover, the measurement results demonstrate that more than 11 504 RFFs among the generated patterns can be classified with an accuracy exceeding 99%.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"83-96"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10660491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142235709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking 通过参考电导跟踪进行漂移补偿的基于 PCM 的模拟内存计算读出方案

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-07-25 DOI: 10.1109/OJSSCS.2024.3432468

Alessio Antolini;Andrea Lico;Francesco Zavalloni;Eleonora Franchi Scarselli;Antonio Gnudi;Mattia Luigi Torres;Roberto Canegallo;Marco Pasotti

{"title":"A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking","authors":"Alessio Antolini;Andrea Lico;Francesco Zavalloni;Eleonora Franchi Scarselli;Antonio Gnudi;Mattia Luigi Torres;Roberto Canegallo;Marco Pasotti","doi":"10.1109/OJSSCS.2024.3432468","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3432468","url":null,"abstract":"This article presents a readout scheme for analog in-memory computing (AIMC) based on an embedded phase-change memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the phase-change memory (PCM) devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions and show that the mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-h bake at \u0000<inline-formula> <tex-math>$85~{^{circ }}$ </tex-math></inline-formula>\u0000C. Based on several MAC operations, the estimated \u0000<inline-formula> <tex-math>$512times 512$ </tex-math></inline-formula>\u0000 matrix-vector-multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"69-82"},"PeriodicalIF":0.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Speed Wireline Links—Part I: Modeling 高速有线链路--第一部分：建模

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-07-24 DOI: 10.1109/OJSSCS.2024.3433324

Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami

引用次数: 0

High-Speed Wireline Links—Part II: Optimization and Performance Assessment 高速有线链路--第二部分：优化和性能评估

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-07-01 DOI: 10.1109/OJSSCS.2024.3421868

Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami

引用次数: 0