IEEE Open Journal of the Solid-State Circuits Society最新文献

{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2025.3534449","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3534449","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143848774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LTPO-TFT-Based Pixel Circuit With TFT, OLED, and Supply Voltage Compensation for Enhanced Luminance Uniformity in Variable-Frame-Rate AMOLED Smartwatch Displays","authors":"Jui-Hung Chang;Cheng-Han Ke;Chia-Lun Lee;Po-Cheng Lai;Chi-Hsuan Huang;Li-Wei Shih;Chih-Lung Lin","doi":"10.1109/OJSSCS.2025.3560242","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3560242","url":null,"abstract":"This work proposes a new pixel circuit using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs) for use in variable-frame-rate active-matrix organic light-emitting diode (AMOLED) smartwatch displays. The proposed circuit, including seven TFTs and two capacitors, can compensate for threshold voltage (<inline-formula> <tex-math>$V_{mathrm { TH}}$ </tex-math></inline-formula>) variations of the driving TFTs (DTFTs), the turn-on voltages of the OLEDs (<inline-formula> <tex-math>$V_{mathrm { OLED}}$ </tex-math></inline-formula>), and <inline-formula> <tex-math>$V_{mathrm { SS}}$ </tex-math></inline-formula> IR rises; it is immune to <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> IR drops. It employs amorphous-indium-gallium-zinc-oxide (a-IGZO) TFTs, which exhibit low leakage currents, suppressing distortion in the gate voltage of the DTFT at low frame rates and enabling a stable OLED current (<inline-formula> <tex-math>$I_{mathrm { OLED}}$ </tex-math></inline-formula>) to maintain consistent display luminance. A 1.28-In LTPO AMOLED panel with a <inline-formula> <tex-math>$416times 416$ </tex-math></inline-formula> resolution and the proposed pixel circuit are fabricated to verify the circuit’s performance. The experimental results thus obtained confirm that red, green, blue, and white images at frame rates from 45 to 1 Hz exhibit uniformity without visible spot or line defects and a luminance error rate below 2.34%. Measured luminance values remain stable at gray levels of 32, 64, 128, and 255 during an extended emission period of 1 s, revealing no perceived image flicker at 1 Hz (with a Japan Electronics and Information Technology Industries Association flicker value below −54.747 dB). Therefore, the proposed circuit, with its highly uniform and stable currents at various frame rates, is promising for use in AMOLED smartwatch displays.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"130-143"},"PeriodicalIF":0.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963900","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143925088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New Associate Editors","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3540393","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3540393","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"101-103"},"PeriodicalIF":0.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10936518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simultaneous Bidirectional Signaling for Die-to-Die Links: Signal Integrity Challenges and Hybrid Circuits","authors":"Durand Jarrett-Amor;Tony Chan Carusone","doi":"10.1109/OJSSCS.2025.3546889","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3546889","url":null,"abstract":"This article reviews simultaneous bidirectional signaling and its unique signal integrity challenges for die-to-die links: the near-end echo signal and the hybrid circuit required to remove it, signal reflections, and the impact of timing. A few key works in the design of simultaneous bidirectional transceivers are covered, such as dynamic reference-switching, the replica driver, and the split-termination hybrid, followed by a survey of recent simultaneous bidirectional transceivers for die-to-die links. Finally, we present our own split-termination, passive hybrid simultaneous bidirectional transceiver as a low-power alternative for die-to-die links.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"116-129"},"PeriodicalIF":0.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10907904","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2024 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 4","authors":"","doi":"10.1109/OJSSCS.2025.3545275","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3545275","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"381-390"},"PeriodicalIF":0.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial Message From the Incoming Editor-in-Chief","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3526922","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526922","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"378-378"},"PeriodicalIF":0.0,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10896768","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial Special section on High-Performance Wireline Transceiver Circuits","authors":"Sam Palermo;Jaeduk Han","doi":"10.1109/OJSSCS.2025.3526924","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526924","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"379-380"},"PeriodicalIF":0.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wideband Continuous-Time MASH ADCs: Principles, Challenges, and Prospects","authors":"Ke Li;Liang Qi;Mingqiang Guo;Rui P. Martins;Sai-Weng Sin","doi":"10.1109/OJSSCS.2025.3543761","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3543761","url":null,"abstract":"Continuous-time (CT) delta-sigma modulator (DSM) is a popular choice for its inherent aliasing and resistive input impedance characteristics. With the increased demands for wide-bandwidth (BW) and high-dynamic range (DR), multistage noise shaping (MASH) presents prominent benefits of high-order noise-shaping (NS) without being constrained by <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> loop stability issues. Recent literature on CT MASH DSM showed promising progress in overcoming the design challenges under wideband application, including signal and quantization leakage, analog-digital matching complexity, signal transfer function (STF) peaking, and high-speed excess loop delay (ELD) compensation. This review article introduces fundamental models and primary design considerations, then discusses the CT MASH DSM’s key challenges and corresponding solutions. Finally, we provide two implementation examples of this architecture with their highlights and challenges.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"104-115"},"PeriodicalIF":0.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892233","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial Special Section on High-Performance Frequency Synthesizers","authors":"Salvatore Levantino;Wanghua Wu","doi":"10.1109/OJSSCS.2025.3526923","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526923","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"376-377"},"PeriodicalIF":0.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877780","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143360883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology","authors":"Rajiv V. Joshi;J. Frougier;Alberto Cestero;Crystal Castellanos;Sudipto Chakraborty;Carl Radens;M. Silvestre;S. Lucarini;I. Ahsan;E. Leobandung","doi":"10.1109/OJSSCS.2024.3524495","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3524495","url":null,"abstract":"A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—<inline-formula> <tex-math>$0.026~mu $ </tex-math></inline-formula>m², and high current—<inline-formula> <tex-math>$0.032~mu $ </tex-math></inline-formula>m²).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"60-74"},"PeriodicalIF":0.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839490","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143388591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}