{"title":"用于端到端集成电路控制的0.45 mm²3.49-TOPS/W低温深度强化学习模块","authors":"Jiachen Xu;John Kan;Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3601153","DOIUrl":null,"url":null,"abstract":"This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-<inline-formula> <tex-math>${\\mathrm { mm}}^{2}$ </tex-math></inline-formula> core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of <inline-formula> <tex-math>$4.925~\\mu $ </tex-math></inline-formula>s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K (<inline-formula> <tex-math>$85~^{\\circ }$ </tex-math></inline-formula>C) to 4.2 K (–<inline-formula> <tex-math>$269~^{\\circ }$ </tex-math></inline-formula>C).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"240-250"},"PeriodicalIF":3.2000,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11133470","citationCount":"0","resultStr":"{\"title\":\"A 0.45-mm² 3.49-TOPS/W Cryogenic Deep Reinforcement Learning Module for End-to-End Integrated Circuits Control\",\"authors\":\"Jiachen Xu;John Kan;Yuyi Shen;Ethan Chen;Vanessa Chen\",\"doi\":\"10.1109/OJSSCS.2025.3601153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-<inline-formula> <tex-math>${\\\\mathrm { mm}}^{2}$ </tex-math></inline-formula> core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of <inline-formula> <tex-math>$4.925~\\\\mu $ </tex-math></inline-formula>s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K (<inline-formula> <tex-math>$85~^{\\\\circ }$ </tex-math></inline-formula>C) to 4.2 K (–<inline-formula> <tex-math>$269~^{\\\\circ }$ </tex-math></inline-formula>C).\",\"PeriodicalId\":100633,\"journal\":{\"name\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"volume\":\"5 \",\"pages\":\"240-250\"},\"PeriodicalIF\":3.2000,\"publicationDate\":\"2025-08-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11133470\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11133470/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11133470/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.45-mm² 3.49-TOPS/W Cryogenic Deep Reinforcement Learning Module for End-to-End Integrated Circuits Control
This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-${\mathrm { mm}}^{2}$ core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of $4.925~\mu $ s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K ($85~^{\circ }$ C) to 4.2 K (–$269~^{\circ }$ C).