Fast-Locking and High-Resolution DLL With Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS

Abstract

This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog converter (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the BS controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75-V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed design achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking and resolution FoM of 0.01 pJ $\cdot $ ns2.