IEEE Open Journal of the Solid-State Circuits Society最新文献_第10页

A Spurless and Wideband Continuous-Time Electro-Optical Phase Locked Loop (CT-EOPLL) for High Performance LiDAR 用于高性能激光雷达的无杂散宽带连续时间电光锁相环（CT-EOPLL）

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-15 DOI: 10.1109/OJSSCS.2021.3120243

Ali Binaie;Sohail Ahasan;Harish Krishnaswamy

{"title":"A Spurless and Wideband Continuous-Time Electro-Optical Phase Locked Loop (CT-EOPLL) for High Performance LiDAR","authors":"Ali Binaie;Sohail Ahasan;Harish Krishnaswamy","doi":"10.1109/OJSSCS.2021.3120243","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3120243","url":null,"abstract":"Frequency-modulated continuous-wave (FMCW) LiDAR systems are drawing increasing interest due to their potential applications in autonomous driving, machine perception, rapid prototyping, and medical diagnostics. The nonlinearity of a laser’s input-output transfer function can degrade the performance of an FMCW LiDAR. However, traditional discrete-time electro-optical phase-locked loops (DT-EOPLLs) face an unfavorable trade-off between chirp bandwidth and Mach-Zehnder delay. We present an integrated continuous-time electro-optic phase-locked loop (CT-EOPLL) to address this problem. The proposed EOPLL is very wideband, with its loop bandwidth equal to its reference frequency. This feature enables it to relax the trade-off between chirp bandwidth and Mach-Zehnder (MZ) delay by \u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 in dB scale, which consequently reduces the area and loss associated with the silicon photonic delay implementation. It also does not suffer from the challenging issue of spurs in wideband PLLs because it features image and harmonic spur suppression in the loop using single-sideband (SSB) and harmonic-reject (HR) mixing techniques. The electrical part of this EOPLL is implemented in 65nm CMOS technology, and its optical integrated circuit is fabricated using a silicon photonic process. Featuring more than 25dB of suppression of the highest spur, this EOPLL is utilized in a high precision LiDAR sensor that shows an RMS depth precision of \u0000<inline-formula> <tex-math>$558~mu text{m}$ </tex-math></inline-formula>\u0000 at 2m distance, and a 9.4mm RMS depth resolution at ranges exceeding 3.3m.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"235-246"},"PeriodicalIF":0.0,"publicationDate":"2021-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09576527.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Review of Semiconductor-Based Monolithic Optical Phased Array Architectures 半导体单片光学相控阵结构综述

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-15 DOI: 10.1109/OJSSCS.2021.3120238

Hossein Hashemi

引用次数: 5

An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training 用于设备上深度神经网络训练的节能硬件加速器综述

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-13 DOI: 10.1109/OJSSCS.2021.3119554

Jinsu Lee;Hoi-Jun Yoo

{"title":"An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training","authors":"Jinsu Lee;Hoi-Jun Yoo","doi":"10.1109/OJSSCS.2021.3119554","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3119554","url":null,"abstract":"Deep Neural Networks (DNNs) have been widely used in various artificial intelligence (AI) applications due to their overwhelming performance. Furthermore, recently, several algorithms have been reported that require on-device training to deliver higher performance in real-world environments and protect users’ personal data. However, edge/mobile devices contain only limited computation capability with battery power, so an energy-efficient DNN training processor is necessary to realize on-device training. Although there are a lot of surveys on energy-efficient DNN inference hardware, the training is quite different from the inference. Therefore, analysis and optimization techniques targeting DNN training are required. This article aims to provide an overview of energy-efficient DNN processing that enables on-device training. Specifically, it will provide hardware optimization techniques to overcomes the design challenges in terms of distinct dataflow, external memory access, and computation. In addition, this paper summarizes key schemes of recent energy-efficient DNN training ASICs. Moreover, we will also show a design example of DNN training ASIC with energy-efficient optimization techniques.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"115-128"},"PeriodicalIF":0.0,"publicationDate":"2021-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09569757.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier 噪声整形SAR ADC综述：从基础到前沿

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-13 DOI: 10.1109/OJSSCS.2021.3119910

Lu Jie;Xiyuan Tang;Jiaxin Liu;Linxiao Shen;Shaolan Li;Nan Sun;Michael P. Flynn

引用次数: 11

A High-Throughput Photon Processing Technique for Range Extension of SPAD-Based LiDAR Receivers 一种用于SPAD激光雷达接收机增程的高通量光子处理技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-11 DOI: 10.1109/OJSSCS.2021.3118987

Sarrah M. Patanwala;Istvan Gyongy;Hanning Mai;Andreas Aßmann;Neale A. W. Dutton;Bruce R. Rae;Robert K. Henderson

引用次数: 18

Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs 高分辨率混合离散时间噪声整形ADC的最新进展

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-08 DOI: 10.1109/OJSSCS.2021.3118668

Dongyang Jiang;Sai-Weng Sin;Liang Qi;Guoxing Wang;Rui P. Martins

引用次数: 4

A 240 × 160 3D-Stacked SPAD dToF Image Sensor With Rolling Shutter and In-Pixel Histogram for Mobile Devices 用于移动设备的具有滚动快门和像素内直方图的240×160三维堆叠SPAD dToF图像传感器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-08 DOI: 10.1109/OJSSCS.2021.3118332

Chao Zhang;Ning Zhang;Zhijie Ma;Letian Wang;Yu Qin;Jieyang Jia;Kai Zang

{"title":"A 240 × 160 3D-Stacked SPAD dToF Image Sensor With Rolling Shutter and In-Pixel Histogram for Mobile Devices","authors":"Chao Zhang;Ning Zhang;Zhijie Ma;Letian Wang;Yu Qin;Jieyang Jia;Kai Zang","doi":"10.1109/OJSSCS.2021.3118332","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118332","url":null,"abstract":"A 240 \u0000<inline-formula> <tex-math>$times$ </tex-math></inline-formula>\u0000 160 single-photon avalanche diode (SPAD) sensor integrated with a 3D-stacked 65nm/65nm CMOS technology is reported for direct time-of-flight (dToF) 3D imaging in mobile devices. The top tier is occupied by backside illuminated SPADs with 16 \u0000<inline-formula> <tex-math>$mu {mathrm{ m}}$ </tex-math></inline-formula>\u0000 pitch and 49.7% fill-factor. The SPADS consists of multiple 16\u0000<inline-formula> <tex-math>$times$ </tex-math></inline-formula>\u000016 SPADs top groups, in which each of 8 \u0000<inline-formula> <tex-math>$times$ </tex-math></inline-formula>\u0000 8 SPADs sub-group shares a 10-bit, 97.65ps and 100ns range time-to-digital converter (TDC) in a quad-partition rolling shutter mode. During the exposure of each rolling stage, partial histogramming readout (PHR) approach is implemented to compress photon events to in-pixel histograms. Since the fine histograms is incomplete, for the first time we propose histogram distortion correction (HDC) algorithm to solve the linearity discontinuity at the coarse bin edges. With this algorithm, depth measurement up to 9.5m achieves an accuracy of 1cm and precision of 9mm in office lighting condition. Outdoor measurement with 10 klux sunlight achieves a maximum distance detection of 4m at 20 fps, using a VCSEL laser with the average power of 90 mW and peak power of 15 W.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"3-11"},"PeriodicalIF":0.0,"publicationDate":"2021-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09565145.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Lab-on-Chip for Everyone: Introducing an Electronic-Photonic Platform for Multiparametric Biosensing Using Standard CMOS Processes 人人共享的片上实验室：介绍一种使用标准CMOS工艺进行多参数生物传感的电子光子平台

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-07 DOI: 10.1109/OJSSCS.2021.3118336

Christos Adamopoulos;Panagiotis Zarkos;Sidney Buchbinder;Pavan Bhargava;Ali Niknejad;Mekhail Anwar;Vladimir Stojanović

{"title":"Lab-on-Chip for Everyone: Introducing an Electronic-Photonic Platform for Multiparametric Biosensing Using Standard CMOS Processes","authors":"Christos Adamopoulos;Panagiotis Zarkos;Sidney Buchbinder;Pavan Bhargava;Ali Niknejad;Mekhail Anwar;Vladimir Stojanović","doi":"10.1109/OJSSCS.2021.3118336","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118336","url":null,"abstract":"The recent pandemic has shown that accurate and on-demand information on various infections requires highly versatile, Point-of-Care (PoC) platforms providing diagnostic and prognostic multiparametric information, personalized to each patient. Despite the significant progress made over the last years in various biosensing technologies, existing solutions fail to meet the power and area requirements needed for highly scalable and portable next-generation PoC devices. This work presents a solution based on a first of its kind fully integrated electronic-photonic platform in a zero-change high volume CMOS-SOI process, tailored towards molecular and ultrasound sensing applications. Leveraging co-integration of \u0000<inline-formula> <tex-math>$10mu text{m}$ </tex-math></inline-formula>\u0000 micro-ring resonators (MRRs) with on-chip electronics, we address the current needs of scalability, power and area by providing nanophotonic sensing and readout processing on a monolithic electronic-photonic system-on-chip (EPSoC). This work unlocks the door towards complete and self-contained Lab-on-Chip (LoC) systems, capable of providing multiparametric biosensing information.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"198-208"},"PeriodicalIF":0.0,"publicationDate":"2021-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09563081.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Low Power Clock Generator Design With CMOS Signaling 低功耗CMOS信号时钟发生器的设计

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-07 DOI: 10.1109/OJSSCS.2021.3118339

Yongping Fan;Ian A. Young

{"title":"Low Power Clock Generator Design With CMOS Signaling","authors":"Yongping Fan;Ian A. Young","doi":"10.1109/OJSSCS.2021.3118339","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118339","url":null,"abstract":"The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"162-170"},"PeriodicalIF":0.0,"publicationDate":"2021-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09563068.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design Methodologies for Low-Jitter CMOS Clock Distribution 低抖动CMOS时钟分布的设计方法

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-10-05 DOI: 10.1109/OJSSCS.2021.3117930

Xunjun Mo;Jiaqi Wu;Nijwm Wary;Tony Chan Carusone

引用次数: 1