Sparsity-Aware 25-Gb/s Memory Link With 0.0375-pJ/bit Signaling Efficiency for Machine Learning Hardware

Abstract

This work describes a multiplication and accumulation (MAC) accelerator integrated with a memory interface. The link is designed to take advantage of naturally existing sparsity in a neural network. The link operating at 16 Gb/s achieves 0.1875-pJ/bit signaling efficiency for random data but, for sparse data, signaling efficiency can improve to 0.0375 pJ/bit. Similarly, the MAC unit accelerates the computation utilizing the phase domain accumulation process and provides a 40% improvement in energy efficiency for sparse data and at the same achieves inference accuracy of 94% for the MNIST data set.