IEEE Open Journal of the Solid-State Circuits Society最新文献

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A 0.69-mW Subsampling NB-IoT Receiver Employing a Linearized Q-Boosted LNA 采用线性化 Q 升压低噪声放大器的 0.69 毫瓦采样 NB-IoT 接收器
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-06-19 DOI: 10.1109/OJSSCS.2024.3416893
Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier
{"title":"A 0.69-mW Subsampling NB-IoT Receiver Employing a Linearized Q-Boosted LNA","authors":"Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier","doi":"10.1109/OJSSCS.2024.3416893","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3416893","url":null,"abstract":"This article presents a receiver for narrowband IoT (NB-IoT) that eliminates the need for an RF local oscillator (LO) via a subsampling architecture. A pseudo-balun Q-boosted LNA provides sharp anti-aliasing filtering with a noise figure (NF) of 5.6 dB. A direct-coupling derivative superposition technique where low-\u0000<inline-formula> <tex-math>$V_{t}$ </tex-math></inline-formula>\u0000 and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to −18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"57-68"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10564201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL A-102 dBm 灵敏度、集成 ADPLL 的多通道异频唤醒接收器
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-04-10 DOI: 10.1109/OJSSCS.2024.3387388
Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers
{"title":"A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL","authors":"Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers","doi":"10.1109/OJSSCS.2024.3387388","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3387388","url":null,"abstract":"This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–\u0000<inline-formula> <tex-math>$171~mu $ </tex-math></inline-formula>\u0000A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"43-56"},"PeriodicalIF":0.0,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496457","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140902616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Open Journal of the Solid-State Circuits Society IEEE 固态电路学会公开期刊
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-01-04 DOI: 10.1109/OJSSCS.2023.3346008
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2023.3346008","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3346008","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10381509","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139109689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Open Journal of the Solid-State Circuits Society Information for Authors IEEE 固态电路学会公开期刊 作者须知
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-12-22 DOI: 10.1109/OJSSCS.2023.3346150
{"title":"IEEE Open Journal of the Solid-State Circuits Society Information for Authors","authors":"","doi":"10.1109/OJSSCS.2023.3346150","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3346150","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"C3-C4"},"PeriodicalIF":0.0,"publicationDate":"2023-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10371322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Survey of Computing-in-Memory Processor: From Circuit to Application 内存计算处理器概览:从电路到应用
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-12-22 DOI: 10.1109/OJSSCS.2023.3328290
Wenyu Sun;Jinshan Yue;Yifan He;Zongle Huang;Jingyu Wang;Wenbin Jia;Yaolei Li;Luchang Lei;Hongyang Jia;Yongpan Liu
{"title":"A Survey of Computing-in-Memory Processor: From Circuit to Application","authors":"Wenyu Sun;Jinshan Yue;Yifan He;Zongle Huang;Jingyu Wang;Wenbin Jia;Yaolei Li;Luchang Lei;Hongyang Jia;Yongpan Liu","doi":"10.1109/OJSSCS.2023.3328290","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3328290","url":null,"abstract":"The computing-in-memory (CIM) technique is emerging with the evolvement of big data and artificial intelligence (AI) application. The manuscript presents a systematic review of existing CIM works in a bottom-up view from circuit to application. Various types of CIM circuits based on different volatile/nonvolatile devices are introduced. The micro CIM architectures are illustrated to support multibit precision computation. After that, several types of processor-level CIM chips are analyzed to reveal the system architecture design considerations. The corresponding CIM tool chains and applications beyond AI applications are also introduced. From circuit to application levels, this manuscript analyzes the design tradeoffs, remained challenges, and possible future design trends at different design hierarchies of CIM processors.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"25-42"},"PeriodicalIF":0.0,"publicationDate":"2023-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10371329","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Editorial OJ-SSCS Special Issue on Low-Power RF Circuits and Systems 编辑 OJ-SSCS 低功耗射频电路与系统特刊
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-12-21 DOI: 10.1109/OJSSCS.2023.3338431
Patrick P. Mercier;Steven M. Bowers
{"title":"Editorial OJ-SSCS Special Issue on Low-Power RF Circuits and Systems","authors":"Patrick P. Mercier;Steven M. Bowers","doi":"10.1109/OJSSCS.2023.3338431","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3338431","url":null,"abstract":"Radios are everywhere. They allow us to watch terrestrial TV broadcasts, connect our cars to satellite-based navigation systems, and connect our computers, phones, and other smart devices to the Internet. As the Internet of Things continues to proliferate, radios will start to connect food packaging, pets, environmental monitors, and all sorts of other things to the Internet as well. A large percentage of these emerging applications will operate on either very small batteries or small energy harvesters, and thus must support all application requirements on very tight power budgets. Since radios often dominate the power consumption of low-power sensing nodes, anything we can do to help reduce the power consumption of wireless communications will help enable these new applications. Of course, this should be accomplished thoughtfully, with careful consideration of coexistence, standards, regulations, security, privacy, and other application-level constraints.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"223-224"},"PeriodicalIF":0.0,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10368310","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Overview of Hybrid DC–DC Converters: From Seeds to Leaves 混合直流-直流转换器概述:从种子到树叶
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-11-20 DOI: 10.1109/OJSSCS.2023.3334228
Yan Lu;Junwei Huang;Zhiguo Tong;Tingxu Hu;Wen-Liang Zeng;Mo Huang;Xiangyu Mao;Guigang Cai
{"title":"An Overview of Hybrid DC–DC Converters: From Seeds to Leaves","authors":"Yan Lu;Junwei Huang;Zhiguo Tong;Tingxu Hu;Wen-Liang Zeng;Mo Huang;Xiangyu Mao;Guigang Cai","doi":"10.1109/OJSSCS.2023.3334228","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3334228","url":null,"abstract":"With the surging demands for higher current at sub-1-V supply level in high-performance digital systems, high-efficiency and high-current-density power converters are essential for system integration. Higher voltage supply buses are emerging for high-current applications to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point of load (PoL). Meanwhile, battery-powered portable or wearable devices favor extremely high-power-density solutions, calling for novel power conversion topologies, which have been the hottest topic in the power management IC area in the past decade. This article reviews the switched-capacitor-inductor (SCI) hybrid dc–dc buck converters from the topology “seeds” to their “leaves.” Here, we define six seeds, they are: 1) three-level buck; 2) double-step down buck; 3) inductor-first buck; 4) always-dual-path buck; 5) buck–buck; and 6) multiple-output hybrid buck. We try to analyze and summarize their pros and cons, and to derive the evolution of the hybrid dc–dc converters, with milestone examples. Then, we share our observations, design intuitions, and suggestions to help the researchers and engineers to pick up and design a new SCI hybrid dc–dc converter.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"12-24"},"PeriodicalIF":0.0,"publicationDate":"2023-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10323295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Terahertz Light-Field Imaging With Silicon Technologies 利用硅技术进行太赫兹光场成像
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-10-31 DOI: 10.1109/OJSSCS.2023.3328975
U. R. Pfeiffer;A. Kutaish
{"title":"Terahertz Light-Field Imaging With Silicon Technologies","authors":"U. R. Pfeiffer;A. Kutaish","doi":"10.1109/OJSSCS.2023.3328975","DOIUrl":"10.1109/OJSSCS.2023.3328975","url":null,"abstract":"The terahertz (THz) frequency range is widely considered the most challenging and underdeveloped frequency range due to the lack of technologies to effectively bridge the transition region between microwaves (below 100 GHz) and optics (above 10 000 GHz). Although THz radiation would be perfect for material identification and as a safe alternative to X-rays for producing high-resolution images of the interior of opaque objects, first a fundamentally new approach is needed to establish novel devices and techniques.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"1-11"},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10302341","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135263571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical-Layer Security for Energy-Constrained Integrated Systems: Challenges and Design Perspectives 能源受限集成系统的物理层安全性:挑战与设计视角
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-10-25 DOI: 10.1109/OJSSCS.2023.3327326
Alperen Yasar;Rabia Tugce Yazicigil
{"title":"Physical-Layer Security for Energy-Constrained Integrated Systems: Challenges and Design Perspectives","authors":"Alperen Yasar;Rabia Tugce Yazicigil","doi":"10.1109/OJSSCS.2023.3327326","DOIUrl":"10.1109/OJSSCS.2023.3327326","url":null,"abstract":"The expanding scale and growing connectivity of Internet of Things (IoT) devices coincide with the emergence of next-generation communication technologies. These devices serve various purposes, including communication, manufacturing, biomedical, and environmental monitoring. However, the increasing number of connected devices raises concerns about data security and integrity. Previous research has highlighted the severe consequences of security inadequacies, shown by incidents involving biomedical devices \u0000<xref>[1]</xref>\u0000, \u0000<xref>[2]</xref>\u0000, \u0000<xref>[3]</xref>\u0000 as an example. Nevertheless, due to resource constraints like power, hardware complexity, and latency, digital cryptography is not universally suitable for these devices \u0000<xref>[4]</xref>\u0000, \u0000<xref>[5]</xref>\u0000, \u0000<xref>[6]</xref>\u0000. An alternative is embedding physical-layer security (PLS) measures. Diverse countermeasures within the physical layer have been explored, including wireless network security \u0000<xref>[4]</xref>\u0000, \u0000<xref>[5]</xref>\u0000, \u0000<xref>[6]</xref>\u0000, \u0000<xref>[7]</xref>\u0000, \u0000<xref>[8]</xref>\u0000, \u0000<xref>[9]</xref>\u0000 and resistance against side-channel attacks (SCAs) \u0000<xref>[10]</xref>\u0000, \u0000<xref>[11]</xref>\u0000, \u0000<xref>[12]</xref>\u0000. This study reviews threat modeling for PLS, underlining its significance and emphasizing its similarities and distinctions from conventional security threat models. We then investigate two commonly employed adversarial techniques: 1) eavesdropping and 2) SCAs. This exploration involves an investigation of distinct security approaches, alongside an evaluation of their associated threat models and tradeoffs. While PLS techniques address the aforementioned resource and latency constraints, they do not universally apply to all devices. Ultralow-power or ultralow-latency devices might necessitate balancing security with performance. However, the absence of a standardized framework in the realm of PLS poses challenges for designers in comparing and selecting the most fitting approach. To conclude, this work provides suggestions for addressing current gaps and enhancing the field of PLS.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"262-273"},"PeriodicalIF":0.0,"publicationDate":"2023-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10296525","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135159133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.4-GHz Wideband Wireless Harvester With Integrated Autonomous RF Input-Frequency Tracking for FCC-Compatible Chip-Scale Battery Charging 集成自主射频输入频率跟踪功能的 2.4 GHz 宽带无线采集器,用于 FCC 兼容芯片级电池充电
IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-10-11 DOI: 10.1109/OJSSCS.2023.3323913
Kamala Raghavan Sadagopan;Arun Natarajan
{"title":"A 2.4-GHz Wideband Wireless Harvester With Integrated Autonomous RF Input-Frequency Tracking for FCC-Compatible Chip-Scale Battery Charging","authors":"Kamala Raghavan Sadagopan;Arun Natarajan","doi":"10.1109/OJSSCS.2023.3323913","DOIUrl":"10.1109/OJSSCS.2023.3323913","url":null,"abstract":"RF-powered Internet of Things (IoT) sensor duty cycles are limited due to low available energy at long range in the absence of a battery. Additionally, RF energy harvesters with high-\u0000<inline-formula> <tex-math>$Q$ </tex-math></inline-formula>\u0000 interfaces between the antenna and rectifier suffer from poor sensitivity for RF input frequencies outside their narrow bandwidth. In this article, we address these challenges and present a channel-agnostic far-field 2.4-GHz energy harvester achieving: 1) dynamic RF input frequency tracking for wideband sensitivity; 2) FCC-compatible frequency-hopped input harvesting; and 3) optimal battery charging capability for powering energy-constrained IoT applications. An enhanced antenna-rectifier interface is designed with 2-dB better stand-alone sensitivity and \u0000<inline-formula> <tex-math>$5times $ </tex-math></inline-formula>\u0000 lower leakage using a bulk-connected rectifier. Input frequency tracking is achieved over 15-MHz bandwidth using a fast-settling auto-zeroing amplifier that senses the rectifier’s first-stage output. Chip-scale pulsed battery charging is achieved from cold-start over \u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 RF available power ranging from −27 to −17 dBm with > 22% efficiency across the entire range. State-of-the-art battery charging is achieved at −21.5-dBm incident power and 4.18% duty cycled (1-h-per-day charging) FCC-compliant frequency-hopped RF input assuming a steady-state 100-nA load. The compact harvester IC occupies 2 mm2 in a 65-nm CMOS technology and the antenna and IC integrated together in a chip-on-board approach occupy 2.125 cm2 of PCB area.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"249-261"},"PeriodicalIF":0.0,"publicationDate":"2023-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10278207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136257139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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