IEEE Open Journal of the Solid-State Circuits Society最新文献_第2页

Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers 数据中心高速短距离光互连技术研究进展

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2025-01-06 DOI: 10.1109/OJSSCS.2025.3526132

Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue

{"title":"Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers","authors":"Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue","doi":"10.1109/OJSSCS.2025.3526132","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526132","url":null,"abstract":"The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"86-100"},"PeriodicalIF":0.0,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10824885","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

How to Design a Differential CMOS LC Oscillator 如何设计差分CMOS LC振荡器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-31 DOI: 10.1109/OJSSCS.2024.3524493

Asad A. Abidi;David Murphy

引用次数: 0

A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC 一种13.2 fj /Step 74.3 db SNDR流水线噪声整形SAR+VCO ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-26 DOI: 10.1109/OJSSCS.2024.3523245

Sumukh Prashant Bhanushali;Arindam Sanyal

引用次数: 0

A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS 基于28nm CMOS的70 mhz带宽时间交错噪声整形sar辅助Delta-Sigma数字交叉耦合ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-19 DOI: 10.1109/OJSSCS.2024.3520525

Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx

引用次数: 0

Timing-Skew Calibration Techniques in Time-Interleaved ADCs 时间交错adc的时序倾斜校准技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-17 DOI: 10.1109/OJSSCS.2024.3519486

Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun

引用次数: 0

Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication 高速无线通信中基于cmos的300 ghz收发器的挑战与创新

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-16 DOI: 10.1109/OJSSCS.2024.3519054

Minoru Fujishima

引用次数: 0

A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology −11.6 dbm OMA灵敏度0.55 pj /bit 40gb /s光接收机，采用2端口参数设计方法

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-12-03 DOI: 10.1109/OJSSCS.2024.3510478

Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu

{"title":"A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology","authors":"Yongxin Li;Tianyu Wang;Mostafa Gamal Ahmed;Ruhao Xia;Kyu-Sang Park;Mahmoud A. Khalil;Sashank Krishnamurthy;Zhe Xuan;Ganesh Balamurugan;Pavan Kumar Hanumolu","doi":"10.1109/OJSSCS.2024.3510478","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3510478","url":null,"abstract":"This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 A rms, an averaged INRC density of 6.4 pA/\u0000<inline-formula> <tex-math>$sqrt {text {Hz}}$ </tex-math></inline-formula>\u0000, consumes 11.4 mW of power, and provides 87-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"328-339"},"PeriodicalIF":0.0,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller 基于单片机微环调制器的多目标热控制器发射机

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-27 DOI: 10.1109/OJSSCS.2024.3507754

Ali Sadr;Anthony Chan Carusone

{"title":"A Monolithic Microring Modulator-Based Transmitter With a Multiobjective Thermal Controller","authors":"Ali Sadr;Anthony Chan Carusone","doi":"10.1109/OJSSCS.2024.3507754","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3507754","url":null,"abstract":"This article presents a multiobjective thermal controller that stabilizes the resonance wavelength of silicon photonic microring modulators (MRMs) under varying temperature conditions and fluctuations in laser power. The controller operates in the background while live data is flowing, adjusting the MRM resonance wavelength to achieve optimal application-specific performance metrics, including any one of extinction ratio (ER), optical modulation amplitude (OMA), or level separation mismatch ratio (RLM). This universal bias-assisted photocurrent-based controller is capable of selectively tuning for any of these transmitter metrics without the need for broadband circuits. Notably, this is the first controller proposed to tune the MRM for optimizing RLM, which is particularly important as MRMs are now increasingly adopted for 4-PAM modulation. The controller functionality is verified on an MRM monolithically integrated in a silicon photonic 45-nm CMOS SOI process with a high-swing \u0000<inline-formula> <tex-math>$4.7~{V}_{text {pp}}$ </tex-math></inline-formula>\u0000 digital-to-analog converter (DAC)-based 5.5-bit resolution driver, dissipating \u0000<inline-formula> <tex-math>$1.7~text {pJ/b}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$40~text {Gb/s}$ </tex-math></inline-formula>\u0000. With the controller optimizing for different objectives, an ER of 10.3 dB, OMA of \u0000<inline-formula> <tex-math>$540~mu text {W}$ </tex-math></inline-formula>\u0000 (normallized OMA of −3.2 dB), transmitter dispersion eye closure quaternary (TDECQ) of 0.67 dB, and RLM of 0.96 are achieved without employing a nonlinear feed-forward equalizer (FFE) or predistortion.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"340-350"},"PeriodicalIF":0.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers 基于adc - dsp均衡器的超高速有线接收机的最新进展

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-26 DOI: 10.1109/OJSSCS.2024.3506692

Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim

{"title":"Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers","authors":"Seoyoung Jang;Jaewon Lee;Yujin Choi;Donggeun Kim;Gain Kim","doi":"10.1109/OJSSCS.2024.3506692","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506692","url":null,"abstract":"High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"290-304"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767763","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions AI/ML应用中先进封装技术的高带宽芯片互连：挑战和解决方案

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-26 DOI: 10.1109/OJSSCS.2024.3506694

Shenggao Li;Mu-Shan Lin;Wei-Chih Chen;Chien-Chun Tsai

{"title":"High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions","authors":"Shenggao Li;Mu-Shan Lin;Wei-Chih Chen;Chien-Chun Tsai","doi":"10.1109/OJSSCS.2024.3506694","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3506694","url":null,"abstract":"The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"351-364"},"PeriodicalIF":0.0,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767590","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0