IEEE Open Journal of the Solid-State Circuits Society最新文献_第2页

Si Substrate Backside—An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging 硅衬底背面——倒装封装中安全集成电路的新兴物理攻击面

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-18 DOI: 10.1109/OJSSCS.2024.3499967

Makoto Nagata;Takuji Miki

引用次数: 0

Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications 超过200gb /s的PAM4 ADC和基于dac的有线和线性光学应用收发器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-18 DOI: 10.1109/OJSSCS.2024.3501975

Ahmad Khairi;Amir Laufer;Ilia Radashkevich;Yoel Krupnik;Jihwan Kim;Tali Warshavsky Grafi;Ajay Balankutty;Yaniv Sabag;Yoav Segal;Udi Virobnik;Mike Peng Li;Itamar Levin;Yosef Ben Ezra;Ariel Cohen

{"title":"Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications","authors":"Ahmad Khairi;Amir Laufer;Ilia Radashkevich;Yoel Krupnik;Jihwan Kim;Tali Warshavsky Grafi;Ajay Balankutty;Yaniv Sabag;Yoav Segal;Udi Virobnik;Mike Peng Li;Itamar Levin;Yosef Ben Ezra;Ariel Cohen","doi":"10.1109/OJSSCS.2024.3501975","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3501975","url":null,"abstract":"System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"265-276"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10756610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques 使用参考波形过采样技术的毫米波全数字锁相环

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-11-07 DOI: 10.1109/OJSSCS.2024.3493803

Teerachot Siriburanon;Chunxiao Liu;Jianglin Du;Robert Bogdan Staszewski

{"title":"Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques","authors":"Teerachot Siriburanon;Chunxiao Liu;Jianglin Du;Robert Bogdan Staszewski","doi":"10.1109/OJSSCS.2024.3493803","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3493803","url":null,"abstract":"This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL \u0000<inline-formula> <tex-math>${mathrm {FoM}}_{text {jitter-N}}$ </tex-math></inline-formula>\u0000 of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"212-225"},"PeriodicalIF":0.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10746550","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems 大规模以太网交换系统中基于dsp的112gb /s PAM-4收发器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-10-30 DOI: 10.1109/OJSSCS.2024.3488654

Henry Park;Mohammed Abdullatif;Ehung Chen;Tamer Ali

引用次数: 0

The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation 5G FR2 相控阵中的杂散发射问题，以及基于嵌入式 LO 漏泄消除的上混频器的解决方案

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-10-28 DOI: 10.1109/OJSSCS.2024.3487548

Arun Paidimarri;Yujiro Tojo;Caglar Ozdag;Alberto Valdes-Garcia;Bodhisatwa Sadhu

{"title":"The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation","authors":"Arun Paidimarri;Yujiro Tojo;Caglar Ozdag;Alberto Valdes-Garcia;Bodhisatwa Sadhu","doi":"10.1109/OJSSCS.2024.3487548","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3487548","url":null,"abstract":"The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this article, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meet these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the upmixer. We introduce two actuator circuits to control two independent LO signals at the upmixer output, one resulting from the upconversion from dc to LO, and another resulting from downconversion from 2 LO to LO. These two independent LO outputs then provide 2-D phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the upmixer. The LO cancellation results in better than −57-dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a 60 beam steering range.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"193-211"},"PeriodicalIF":0.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10737135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142679264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation 具有ΔΣ量化抵消的分数- n合成器中的非线性诱导杂散分析

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-10-08 DOI: 10.1109/OJSSCS.2024.3476035

Yizhe Hu;Weichen Tao;Robert Bogdan Staszewski

{"title":"Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation","authors":"Yizhe Hu;Weichen Tao;Robert Bogdan Staszewski","doi":"10.1109/OJSSCS.2024.3476035","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3476035","url":null,"abstract":"A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms,> <tex-math>$(Delta Sigma )$ </tex-math></inline-formula>\u0000 quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"226-237"},"PeriodicalIF":0.0,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10707313","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SAR-Assisted Energy-Efficient Hybrid ADCs SAR 辅助型高能效混合 ADC

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-10-01 DOI: 10.1109/OJSSCS.2024.3472000

Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu

引用次数: 0

Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth 基于系统方程设计具有 2 GHz 分辨率带宽的 10 位 500-MS/s 单通道 SAR A/D 转换器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-26 DOI: 10.1109/OJSSCS.2024.3469109

Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi

引用次数: 0

Digital Phase-Locked Loops: Exploring Different Boundaries 数字锁相环：探索不同的边界

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-20 DOI: 10.1109/OJSSCS.2024.3464551

Yuncheng Zhang;Dingxin Xu;Kenichi Okada

{"title":"Digital Phase-Locked Loops: Exploring Different Boundaries","authors":"Yuncheng Zhang;Dingxin Xu;Kenichi Okada","doi":"10.1109/OJSSCS.2024.3464551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3464551","url":null,"abstract":"This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"176-192"},"PeriodicalIF":0.0,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10684740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142524125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects 数据中心时代的高带宽和高能效存储器接口：最新进展、设计挑战和未来展望

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-11 DOI: 10.1109/OJSSCS.2024.3458900

Joo-Hyung Chae

{"title":"High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects","authors":"Joo-Hyung Chae","doi":"10.1109/OJSSCS.2024.3458900","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3458900","url":null,"abstract":"Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"252-264"},"PeriodicalIF":0.0,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10677348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0