IEEE Open Journal of the Solid-State Circuits Society最新文献_第2页

Integrated Sense-and-React Countermeasures Against Physical Attacks on Resource-Constrained Security Systems 针对资源受限安全系统物理攻击的综合感知与反应对策

IF 3.2

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-12 DOI: 10.1109/OJSSCS.2026.3652562

Noriyuki Miura

{"title":"Integrated Sense-and-React Countermeasures Against Physical Attacks on Resource-Constrained Security Systems","authors":"Noriyuki Miura","doi":"10.1109/OJSSCS.2026.3652562","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3652562","url":null,"abstract":"An integrated sense-and-react countermeasure constitutes a promising hardware-security approach to mitigate malicious physical attacks targeting resource-constrained yet security-critical information systems. An integrated physical-attack sensor detects, in situ, the potential risk of information leakage, and upon detection, an integrated reaction circuit autonomously responds by immediately disabling the attack to protect secret information. To reduce hardware overhead, the sensor and reaction circuits are specifically tailored to the assumed attack surfaces, scenarios, and required security levels. This article presents compact, low-power integrated sensors, and reaction circuits designed to counter both passive side-channel and active fault-injection attacks, such as those exploiting power traces, electromagnetic radiation, and laser-induced faults. Silicon prototypes validate the proposed approach by demonstrating comprehensive attack detection and effective risk mitigation of information leakage, achieved with limited hardware cost, thereby enabling practical deployment in resource-constrained security systems.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"15-24"},"PeriodicalIF":3.2,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11345479","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Overview of Time-Interleaved Noise-Shaping ADCs: Fundamentals, Challenges, and Prospects 时间交错噪声整形adc的概述：基础、挑战和前景

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-02-17 DOI: 10.1109/OJSSCS.2026.3665854

Yuekai Liu;Ziqiang Cai;Yan Liu;Liang Qi

引用次数: 0

Capacitance-to-Digital Converters: Recent Advances and Evolving Trends From Circuit-Level Performances to System Requirements 电容-数字转换器：从电路级性能到系统要求的最新进展和发展趋势

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-04-21 DOI: 10.1109/OJSSCS.2026.3686096

Donghyun Youn;Gichan Yun;Yoontae Jung;Hoyong Seong;Sohmyung Ha;Minkyu Je

{"title":"Capacitance-to-Digital Converters: Recent Advances and Evolving Trends From Circuit-Level Performances to System Requirements","authors":"Donghyun Youn;Gichan Yun;Yoontae Jung;Hoyong Seong;Sohmyung Ha;Minkyu Je","doi":"10.1109/OJSSCS.2026.3686096","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3686096","url":null,"abstract":"This article presents a comprehensive review of capacitance-to-digital converters (CDCs) for capacitive sensor interfaces, combining a historically thorough CDC survey with detailed architectural analysis. Covering over a decade of IEEE-published designs, it introduces key performance metrics of CDC design—energy efficiency, resolution, and input range—across successive approximation register (SAR), delta–sigma modulation (DSM), period modulation (PM), and hybrid architectures, supported by survey plots that reveal existing tradeoffs and design trends. Each topology is examined quantitatively for recent advances that mitigate the tradeoffs between intrinsic energy consumption and noise performance, as well as its remaining circuit-level limitations. Hybrid architectures, which alleviate these limitations while effectively combining the strengths of each topology, are also introduced. In addition, this review provides a detailed comparison of numerical metrics for recent CDC designs, analyzing how each topology improves its characteristic performance and aligns with specific application requirements. Moreover, beyond numerical metrics, it addresses critical system-level considerations, such as stand-alone operation from unregulated supplies, temperature insensitivity, parasitic robustness, and realistic sensor configurations, which are essential for practical CDC deployment. This article concludes by emphasizing the importance of balancing circuit-level performances and system-level requirements in CDC designs to accommodate the increasing significance of capacitive sensor interfaces.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"129-140"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11489322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration 分段线性增益非线性校正的12b 3-GS/s流水线ADC

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-01-23 DOI: 10.1109/OJSSCS.2026.3656850

Mingyang Gu;Yi Zhong;Lu Jie;Nan Sun

引用次数: 0

An LLM Accelerator With Bidirectional Microscaling Quantization 具有双向微尺度量化的LLM加速器

IF 3.2

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-04-28 DOI: 10.1109/OJSSCS.2026.3687842

Yang Zhou;Zhiwei Lin;Yubin Qin;Yang Hu;Yang Wang;Shouyi Yin

{"title":"An LLM Accelerator With Bidirectional Microscaling Quantization","authors":"Yang Zhou;Zhiwei Lin;Yubin Qin;Yang Hu;Yang Wang;Shouyi Yin","doi":"10.1109/OJSSCS.2026.3687842","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3687842","url":null,"abstract":"Large language models (LLMs) have achieved remarkable success across vision, text, and video domains, far surpassing traditional neural networks. However, this success is accompanied by enormous memory access and computational demands. Quantization is a widely used technique to reduce model overhead. Microscaling is a novel fine-grained quantization scheme that employs finer blockwise partitioning, delivering superior performance compared to traditional methods like per-tensor quantization. However, the widespread presence of outliers in models still poses challenges for microscaling quantization. First, a fixed block partitioning pattern with a single dimension cannot adapt to the random distribution of outliers, resulting in degraded quantization performance. Second, outliers within a block cause excessive numerical error in low-bit quantization, forcing the use of higher bit-widths and resulting in wasted power. To address these challenges, first, we propose a bidirectionally partitioned microscaling method that dynamically selects the partitioning direction with fewer outliers. Second, we separate outliers and nonoutliers into sparse and dense data, allowing most nonoutlier data to be quantized to low bit-widths effectively. Third, we designed dense/sparse (D/S) hybrid cores to separately process nonoutlier and outlier data. The experimental results show that our approach reduces the outlier count by 35.9% and memory access by 66.7% on average. The proposed accelerator achieves a peak energy efficiency of 9.81 TFLOPS/W at MXFP4, and outperforms state-of-the-art accelerators with <inline-formula> <tex-math>$1.49times $ </tex-math></inline-formula> lower energy and <inline-formula> <tex-math>$1.38times $ </tex-math></inline-formula> higher speed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"106-117"},"PeriodicalIF":3.2,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11495158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 50-Mb/s Human Body Communication Receiver With 0.7-pJ/b Front-End and Integrating Clock-Data Recovery in 65-nm CMOS 基于65nm CMOS的前端0.7 pj /b、集成时钟数据恢复的50mb /s人体通信接收机

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-08-25 DOI: 10.1109/OJSSCS.2026.3727553

Yudhajit Ray;Samyadip Sarkar;Shreyas Sen

{"title":"A 50-Mb/s Human Body Communication Receiver With 0.7-pJ/b Front-End and Integrating Clock-Data Recovery in 65-nm CMOS","authors":"Yudhajit Ray;Samyadip Sarkar;Shreyas Sen","doi":"10.1109/OJSSCS.2026.3727553","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3727553","url":null,"abstract":"Significant research on developing wireline-like communication has advanced communication energy efficiency from 1 nJ/b to sub-10 pJ/b by utilizing the electro-quasistatic (EQS) nature of the human body at low to medium data rates. However, limited bandwidth and ~68-dB channel loss have hindered this modality in achieving sub-pJ/b energy efficiency. Biophysical investigations of the body channel have led to a more accurate channel model at a relatively higher frequency range where the body exhibits transmission line-like behavior instead of wire-like behavior. This novel communication modality, named body-resonance (BR), offers a wide bandwidth and low channel loss, thereby enhancing channel capacity. This article presents the first IC-measured implementation of an integrating clock data recovery (CDR) for a wearable-to-wearable human body communication (HBC) receiver operating at a data rate of 50 Mb/s. Integrating amplifiers, essential for achieving high energy efficiency, also necessitated a unique CDR architecture. The implementation is fabricated in a 65-nm CMOS technology node and occupies an active area of 0.04 mm2. Furthermore, the integrating receiver, in conjunction with the proposed CDR module, achieves an energy efficiency of 0.7pJ/b (4.5 pJ/b with clock generation) and a bit error rate (BER) of <inline-formula> <tex-math>$10^{-4}$ </tex-math></inline-formula>.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"271-283"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11667019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149188427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and Design of RC-Variation-Robust Continuous-Time Delta-Sigma Modulator With Boosted MSA 增强MSA的rc变差鲁棒连续δ - σ调制器的分析与设计

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-02-03 DOI: 10.1109/OJSSCS.2026.3660214

Zhaonan Lu;Junqi Liu;Liang Qi;Menglian Zhao;Zhichao Tan

{"title":"Analysis and Design of RC-Variation-Robust Continuous-Time Delta-Sigma Modulator With Boosted MSA","authors":"Zhaonan Lu;Junqi Liu;Liang Qi;Menglian Zhao;Zhichao Tan","doi":"10.1109/OJSSCS.2026.3660214","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3660214","url":null,"abstract":"Continuous-time delta-sigma modulators (CT DSMs) have been widely adopted in IoT and sensor applications. Despite the merits of the inherent anti-alias property and easy-driving resistive input, CT DSMs always suffer from the RC variation issue. While a higher maximum stable amplitude (MSA) can result in a higher dynamic range (DR) with better efficiency, it is often limited to −1 dBFS. To address the above issues, this article presents a hybrid 1-2 sturdy multistage noise-shaping (MASH) architecture that exhibits high robustness against RC variations. The proposed modulator integrates a first-order RC-variation-insensitive CT loop filter with a second-order noise-shaping (NS) successive-approximation-register (SAR) quantizer (QTZ). By leveraging the inherent unity signal transfer function (STF) of the NS-SAR QTZ, the quantization noise of the first stage is effectively canceled without requiring analog-to-digital matching. This enables the modulator to achieve a beyond-the-rail MSA while performing aggressive third-order NS. Fabricated in a 55-nm CMOS process, the prototype achieves a measured signal-to-noise-and-distortion ratio (SNDR) of 89.1 dB and a DR of 95.3 dB over a signal bandwidth of 100 kHz while consuming <inline-formula> <tex-math>$459~mu $ </tex-math></inline-formula>W from a single 1.2-V supply. These results yield a state-of-the-art Schreier figure of merit (FoM<inline-formula> <tex-math>${}_{mathrm {S}}$ </tex-math></inline-formula>) of 178.7 dB among prior art with similar bandwidth. Additionally, the prototype demonstrates robust performance across a wide range of temperatures.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"215-225"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11370186","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Beyond Sole Parametric Optimization Design Regimes: Understanding and Advancing the Frontiers of High-Speed ADCs 超越单一参数优化设计体制：理解和推进高速adc的前沿

IF 3.2

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-04-07 DOI: 10.1109/OJSSCS.2026.3681529

Chi-Hang Chan

引用次数: 0

A Pipelined Incremental ΔΣ ADC With Residue Harvesting and Noise Penalty Mitigation 具有残差收集和噪声惩罚抑制的管道式增量ΔΣ ADC

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-02-13 DOI: 10.1109/OJSSCS.2026.3664789

Shih-Che Kuo;Chia-Hung Chen

{"title":"A Pipelined Incremental ΔΣ ADC With Residue Harvesting and Noise Penalty Mitigation","authors":"Shih-Che Kuo;Chia-Hung Chen","doi":"10.1109/OJSSCS.2026.3664789","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3664789","url":null,"abstract":"This article proposes a pipelined incremental analog-to-digital converter (IADC) by cascading two IADCs for a sensor system-on-chip whose oversampling ratio (OSR) is constrained by the system clock frequency. The two-stage IADC disrupts the noise accumulation path of four integrations in a 2-2 multistage noise shaping (MASH) IADC, reducing the noise penalty from fourth order to second order. Consequently, the input sampling capacitor size can be reduced by 42%. Also, the digital filter can be simplified significantly to reduce the overall system-level hardware cost. Two identical integrators are alternating—one integrator accumulates the quantization residue, and the other one holds the residue to interface the second IADC. When one Nyquist conversion is finished, the residue is harvested by one integrator, and these two integrators interchange their roles reciprocally for integration and holding the residue. Additional techniques are proposed to mitigate the circuit nonidealities. The gain self-correction technique eliminates coefficient errors in the first loop, relaxing the matching requirements of the integrator’s coefficient. Furthermore, the dynamically segmented integration combines a static lower bandwidth amplifier with floating inverter amplifiers (FIAs) to accelerate the slewing. Fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m process, the prototyped IADC consumes 0.38 mm2 and <inline-formula> <tex-math>$470~{mathrm {mu }}$ </tex-math></inline-formula>W under a 1.8-V supply. Clocked at 1.6 MHz, it achieves a DR/SNDR of 98.4/95.3 dB over a 20-kHz bandwidth, resulting in FoMS,DR/FoMS,SNDR of 174.7/171.6 dB. This work validates a high-accuracy solution for low OSR applications while maintaining a competitive energy efficiency.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"204-214"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11396019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Input-Driving-Relaxed Noise-Shaping SAR ADC With Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping 具有放大器复用环内缓冲和NTF泄漏整形的输入驱动放松噪声整形SAR ADC

IF 3.7

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2026-01-01 Epub Date: 2026-03-12 DOI: 10.1109/OJSSCS.2026.3673647

Tian Xie;Ken Li;Tzu-Han Wang;Wei-En Lee;Dongsuk Kang;Shaolan Li

{"title":"An Input-Driving-Relaxed Noise-Shaping SAR ADC With Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping","authors":"Tian Xie;Ken Li;Tzu-Han Wang;Wei-En Lee;Dongsuk Kang;Shaolan Li","doi":"10.1109/OJSSCS.2026.3673647","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3673647","url":null,"abstract":"This article presents a third-order noise-shaping successive approximation register (NS SAR) analog-to-digital converter (ADC) with embedded input buffering capability and a PVT robust error-feedback (EF)-based filter. An amplifier-reused in-loop buffering (AILB) architecture is proposed to serve multiple purposes: first, it reuses the residue amplifier for input driving, obviating the need for an explicit buffer and its related noise penalty. Second, it inherently suppresses the sampling kT/C noise without explicit noise-canceling operations. Lastly, it facilitates a simpler bias design compared to using explicit buffers. To enable a PVT-robust EF noise filter, a noise transfer function leakage reshaping (NLRS) technique is proposed, allowing the noise transfer function (NTF) leakage component to be shaped to the first order. Prototyped in 65 nm CMOS technology, this design achieves 82.0 dB signal-to-noise-distortion ratio (SNDR) with 500 kHz bandwidth (BW) under an oversampling ratio (OSR) of 8. The prototype’s total power consumption is <inline-formula> <tex-math>$126.8~mu $ </tex-math></inline-formula>W (including the input driving buffer), achieving a Schreier figure-of-merit (FoM) of 178.0 dB.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"226-237"},"PeriodicalIF":3.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11432886","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0