IEEE Open Journal of the Solid-State Circuits Society最新文献

{"title":"A Current-Mode Multiphase Digital Transmitter With a Single-Footprint Transformer-Based Asymmetric Doherty Output Network","authors":"Jay R. Sheth;Linsheng Zhang;Xiaochuan Shen;Vinay Iyer;Steven M. Bowers","doi":"10.1109/OJSSCS.2023.3290550","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290550","url":null,"abstract":"This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power \u0000<inline-formula> <tex-math>$(P_{mathrm{ out}})$ </tex-math></inline-formula>\u0000 and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a \u0000<inline-formula> <tex-math>$1.76times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.93times $ </tex-math></inline-formula>\u0000 improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average \u0000<inline-formula> <tex-math>$P_{mathrm{ out}}$ </tex-math></inline-formula>\u0000 of 14 dBm with an r.m.s. error vector magnitude \u0000<inline-formula> <tex-math>$({mathrm{ EVM}}_{mathrm{ rms}})$ </tex-math></inline-formula>\u0000 of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"103-117"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167796.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2023.3290551","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3290551","url":null,"abstract":"Wireline receivers continue to target higher data rates, posing great challenges at circuit and architecture levels. Governed by tradeoffs among speed, power consumption, and channel loss (CL), receiver designs can benefit from new methods that push the performance envelope. This paper presents a number of techniques that allow non-return-to-zero data rates as high as 40 and 56 Gb/s in 45-nm and 28-nm CMOS technologies, respectively. The prototypes operate with a CL of 19-25 dB and a bit error rate of less than 10−12.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"118-133"},"PeriodicalIF":0.0,"publicationDate":"2023-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10167779.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2023.3266540","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3266540","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2023-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10101697.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices","authors":"Po-Han Chen;Shu-Wen Yang;Chao-Tsung Huang","doi":"10.1109/OJSSCS.2023.3244759","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3244759","url":null,"abstract":"Digital refocusing in multicamera mobile devices is becoming crucial. Realistic refocusing, which is a subset of digital refocusing, provides physically correct quality; however, its intense computational complexity results in low processing speed and restricts its applicability. Moreover, its complex computation flow requires substantial DRAM bandwidth and a large SRAM area, making it more challenging to implement in hardware. In this article, we present a high-performance refocusing processor based on a hardware-oriented realistic refocusing algorithm. The proposed compact computation flow saves 92% of the DRAM bandwidth and 32% of the SRAM area without noticeable quality degradation. To support high-performance refocusing, we develop highly paralleled engines for view rendering. They deliver 5.4G rendered-pixel/s throughput. The hardware accelerator improves the processing speed by \u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$350times $ </tex-math></inline-formula>\u0000 that of the original refocusing algorithm running on a general-purpose processor. The chip is fabricated with 40-nm CMOS technology and comprises 271 kB of SRAM and 2.3M logic gates. The chip processes Full-HD light fields up to 40 frames/s under 250 mW power consumption.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"52-62"},"PeriodicalIF":0.0,"publicationDate":"2023-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10044201.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synergistic Distributed Thermal Regulation for On-CMOS High-Throughput Multimodal Amperometric DNA-Array Analysis","authors":"Hamed Mazhab Jafari;Xilin Liu;Roman Genov","doi":"10.1109/OJSSCS.2023.3236305","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3236305","url":null,"abstract":"Accurate temperature regulation is critical for amperometric DNA analysis to achieve high fidelity, reliability, and throughput. In this work, a \u0000<inline-formula> <tex-math>$9times 6$ </tex-math></inline-formula>\u0000 cell array of mixed-signal CMOS distributed temperature regulators for on-CMOS multimodal amperometric DNA analysis is presented. Three DNA analysis methods are supported, including constant potential amperometry (CPA), cyclic voltammetry (CV), and impedance spectroscopy (IS). In-cell heating and temperature-sensing elements are implemented in standard CMOS technology without post-processing. Using proportional–integral–derivative (PID) control, the local temperature can be regulated to within ±0.5 °C of any desired value between 20 °C and 90 °C. To allow the in-cell integration of independent PID control, a new mixed-signal design is proposed, where the two computationally intensive operations in the PID algorithm, multiplication and subtraction, are performed by an in-cell dual-slope multiplying ADC, resulting in a small area and low power consumption. Over 95% of the circuit blocks are synergistically shared among the four operating modes, including CPA, CV, IS, and the proposed temperature regulation mode. A 3 mm \u0000<inline-formula> <tex-math>$times3$ </tex-math></inline-formula>\u0000 mm CMOS prototype fabricated in a 0.13-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology has been fully experimentally characterized. The proposed distributed temperature regulation design and the mixed-signal PID implementation can be applied to a wide range of sensory and other applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"89-102"},"PeriodicalIF":0.0,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/10015870.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2023 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 3","authors":"","doi":"10.1109/OJSSCS.2024.3363396","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3363396","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"274-280"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10423723","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Batteryless, Wireless, and Secure SoC for Implantable Strain Sensing","authors":"Mohamed R. Abdelhamid;Unsoo Ha;Utsav Banerjee;Fadel Adib;Anantha P. Chandrakasan","doi":"10.1109/OJSSCS.2022.3230000","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3230000","url":null,"abstract":"The past few years have witnessed a growing interest in wireless and batteryless implants, due to their potential in long-term biomedical monitoring of in-body conditions, such as internal organ movements, bladder pressure, and gastrointestinal health. Early proposals for batteryless implants relied on inductive near-field coupling and ultrasound harvesting, which require direct contact between the external power source and the human body. To overcome this near-field challenge, recent research has investigated the use of RF backscatter in wireless micro-implants because of its ability to communicate with wireless receivers that are placed at a distance outside the body \u0000<inline-formula> <tex-math>$(sim 0.5$ </tex-math></inline-formula>\u0000 m), allowing a more seamless user experience. Unfortunately, existing far-field backscatter designs remain limited in their functionality: they cannot perform biometric sensing or secure data transmission; they also suffer from degraded harvesting efficiency and backscatter range due to the impact of variations in the surrounding tissues. In this article, we present the design of a batteryless, wireless and secure system-on-chip (SoC) implant for in-body strain sensing. The SoC relies on four features: 1) employing a reconfigurable in-body rectenna which can operate across tissues adapting its backscatter bandwidth and center frequency; 2) designing an energy efficient 1.37 mmHg strain sensing front-end with an efficiency of 5.9 mmHg\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000nJ/conversion; 3) incorporating an AES-GCM security engine to ensure the authenticity and confidentiality of sensed data while sharing the ADC with the sensor interface for an area-efficient random number generation; 4) implementing an over-the-air closed-loop wireless programming scheme to reprogram the RF front-end to adapt for surrounding tissues and the sensor front-end to achieve faster settling times below 2 s.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"41-51"},"PeriodicalIF":0.0,"publicationDate":"2022-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09990593.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Integrated Circuits and Systems Based on Thin-Film Transistors","authors":"Kris Myny","doi":"10.1109/OJSSCS.2022.3227060","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3227060","url":null,"abstract":"Thin-Film transistors (TFTs) are ubiquitous today as a backplane technology for various display and imager products. Those transistors act as switches in active-matrix liquid-crystal displays (AM-LCDs) or as full-pixel engines, including driving and threshold compensation, in active-matrix organic light-emitting diodes (AM-OLEDs) panels. TFT manufacturing requires only a limited amount of photolithographic steps, making it a relatively simple transistor technology, compared to the traditional Si CMOS technologies. The processing temperature of TFT technologies is sufficiently low to be compatible with glass and can even enable flexible substrates. Finally, these transistors have been developed specifically for large-area applications, such as televisions and X-ray scanners. Consequently, the backplane size for TFTs has evolved from the generation-1 glass panel of 270 mm by 360 mm to generation-10.5, which is manufactured on a glass panel of 2.94 m \u0000<inline-formula> <tex-math>$times3.37$ </tex-math></inline-formula>\u0000 m \u0000<xref>[1]</xref>\u0000. This is profoundly different from traditional Si CMOS integrated circuits, which are fabricated nowadays on 200 mm or 300 mm round wafers. The critical dimension of the TFT technology on glass or flexible substrate in production is in the range of a few micrometers. The TFT research in the display field focuses on enabling increasingly better pixel resolution, improved visual quality, larger panels for LED walls, flexible displays, camera-behind display, sensor integration, and many more.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"175-176"},"PeriodicalIF":0.0,"publicationDate":"2022-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09985431.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Custom Circuits and Architectures for Energy-Efficient Machine Learning","authors":"Jae-Sun Seo","doi":"10.1109/OJSSCS.2022.3227379","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3227379","url":null,"abstract":"Machine learning (ML) and artificial intelligence (AI) have been successful in many practical applications, e.g., image/speech/video recognition, object detection/tracking, natural language processing, etc. To efficiently execute such AI/ML algorithms, there have been large advances in custom hardware accelerator designs, such as digital systolic arrays of processing engines (PEs), and analog or digital circuits for in-/near-memory computing for deep neural networks (DNNs) \u0000<xref>[1]</xref>\u0000, \u0000<xref>[2]</xref>\u0000.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"217-218"},"PeriodicalIF":0.0,"publicationDate":"2022-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09985421.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Benchmarking In-Memory Computing Architectures","authors":"Naresh R. Shanbhag;Saion K. Roy","doi":"10.1109/OJSSCS.2022.3210152","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3210152","url":null,"abstract":"In-memory computing (IMC) architectures have emerged as a compelling platform to implement energy-efficient machine learning (ML) systems. However, today, the energy efficiency gains provided by IMC designs seem to be leveling off and it is not clear what the limiting factors are. The conceptual complexity of IMCs combined with the absence of a rigorous benchmarking methodology makes it difficult to gauge progress and identify bottlenecks in this exciting field. This article presents a benchmarking methodology for IMCs comprising: 1) a compositional view of IMCs that enables one to parse an IMC design into its canonical components; 2) a set of benchmarking metrics to quantify the performance, efficiency, and accuracy of IMCs; and 3) a strategy for analyzing the reported IMC data and metrics. We apply the proposed benchmarking methodology on an extensive database of IMC metrics extracted from > 70 IC designs published since 2018, in order to infer and comprehend trends in this area. Our benchmarking effort indicates: 1) SRAM-based IMCs show a clear win in terms of energy efficiency and compute density over digital accelerators at the bank level but the energy efficiency gap reduces dramatically when comparing at the processor level; 2) eNVM-based IMCs lag behind SRAM-based IMCs in terms of both energy efficiency and compute density, and surprisingly lag digital accelerators in terms of compute density; 3) the compute (bank-level) accuracy of IMCs, though a critical metric, is pervasively neglected in publications as is the energy versus accuracy tradeoff inherent to IMCs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"288-300"},"PeriodicalIF":0.0,"publicationDate":"2022-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09976888.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50327146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}