IEEE Open Journal of the Solid-State Circuits Society最新文献

{"title":"ATC-Tx: A 21.9 pJ/Sa 110 μW Direct Pixel-to-PWM Converter and Time-Domain Body Communication Transmitter for Video Sensor Nodes","authors":"Gourab Barik;Samyadip Sarkar;Baibhab Chatterjee;Gaurav K. Kumar;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3642795","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3642795","url":null,"abstract":"With the rapid advancement of the Internet of Things (IoT) and its expanding applications in health monitoring, body-worn cameras, and smart glasses, the demand for high data rate (DR) video transmission and compact device size has become critical. This shift has necessitated the development of low-power communication systems and battery-efficient or battery-less designs. Traditional high-data-rate communication methods consume mWs of power, such as Wi-Fi and backscatter communication (for high DRs, higher transmitter power is required to handle the two-fold path loss between the transmitter and sensor node), and require converting analog information into digital bits before transmission. These approaches rely on analog-to-digital converters (ADCs), which generate substantial data volumes, resulting in increased storage and processing demands while consuming significant power <inline-formula> <tex-math>$P_{text {ADC}} propto 2^{N};(text {exponential}) $ </tex-math></inline-formula>, where <inline-formula> <tex-math>$N$ </tex-math></inline-formula> is the number of bits. Consequently, communication power increases <inline-formula> <tex-math>$P_{text {comm}} propto N;(text {linearly})$ </tex-math></inline-formula>, resulting in overall higher power consumption. To address these challenges and reduce the communication energy of a video sensor node (VSN) while enabling a more compact form factor, we propose an analog voltage-to-time converter for VSN (ATC-Tx) that exploits a novel time-domain mode of body communication. This system directly converts analog video information into pulse-width modulated signals for transmission, leveraging the wideband characteristics of the human body communication (HBC) channel as the transmission medium. This approach enables low-power sensing and communication by eliminating the need for ADCs and digitization at energy-constrained VSNs. The ATC-Tx achieves an energy efficiency of 21.9 pJ/Sa, leveraging time-domain body communication (TD-BC), which results in a two-order-of-magnitude improvement over existing commercial off-the-shelf (COTS) components. This improvement is accompanied by a <inline-formula> <tex-math>$sim 3times $ </tex-math></inline-formula> reduction in power consumption compared to the previous voltage mode electro-quasistatic HBC (EQS-HBC)-based implementation, as well as significant reductions in implementation area.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"335-353"},"PeriodicalIF":3.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Implantable Peripheral Nerve Interface System With Simultaneous Multisite Data Transmission via Galvanically Coupled Body-Channel Communication for Next-Generation Prosthetic Limbs","authors":"Dong-Hwi Choi;Dongyoon Lee;Yunchul Chung;Hyunyeop Lee;Kim Hoang Nguyen;Byeongseon Choi;Gichan Yun;Sohmyung Ha;Minkyu Je","doi":"10.1109/OJSSCS.2025.3642787","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3642787","url":null,"abstract":"This article presents a neural implant system for prosthetic limbs that enables simultaneous multisite data transmission via galvanically coupled body-channel communication (GC-BCC) for fine, low-latency control. Ultrasound and RF uplinks typically require multiple-access schemes to avoid collisions across implants. Capacitive BCC can support simultaneous links, but the small, motion-variant return-path capacitance reduces channel gain and undermines robustness. In contrast, GC-BCC forms a closed-loop current path for each transmitter–receiver pair via a dedicated termination, enabling simultaneous uplinks without multiple-access scheme. Implemented in 180-nm CMOS, the system integrates a 16-channel neural recording analog front end, a GC-BCC transceiver, and low-dropout regulators. Through 15-mm porcine tissue, the link sustains a 20-Mb/s data rate with a bit-error rate below <inline-formula> <tex-math>$1.3 times 10^{-5}$ </tex-math></inline-formula>. Two GC-BCC transceivers operate simultaneously with 100-<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> termination with negligible crosstalk at <inline-formula> <tex-math>$geq 1.6$ </tex-math></inline-formula>-cm spacing. The measured energy efficiencies are 20.35 pJ/bit for the transmitter and 467.4 pJ/bit for the receiver.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"324-334"},"PeriodicalIF":3.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293770","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.5 nJ/Conversion Self-Resetting Energy-Autonomous Multi-Node Temperature Sensor With Hybrid Energy Harvesting","authors":"Joanne Si Ying Tan;Zhuoyue Li;Chne-Wuen Tsai;Jeong Hoan Park;Jiamin Li;Yilong Dong;Kwok Hoe Chan;Ghim Wei Ho;Jerald Yoo","doi":"10.1109/OJSSCS.2025.3642796","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3642796","url":null,"abstract":"This article presents an energy-autonomous, self-resetting (SR), and multi-node temperature sensor powered by hybrid energy harvesting (EH). The ultralow leakage self-adaptive full bridge rectifier (SA-FBR) accepts any hybrid EH source at both sparse and abundant inputs and suppresses the leakage by <inline-formula> <tex-math>$1000times $ </tex-math></inline-formula>. The dynamic power management unit (D-PMU) enables event-driven wake-up capability that allows for 97.3% power saving during standby mode. The 0.5 nJ/conversion temperature sensor in <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS uses active SR, spike-based coding to achieve the widest measurement range of –<inline-formula> <tex-math>$10~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$110~^{circ }$ </tex-math></inline-formula>C to date.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"377-387"},"PeriodicalIF":3.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293796","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single-Trim Highly Accurate Frequency Reference Techniques","authors":"Thomas J. Hoen;Alexander S. Delke;Yanyu Jin;Jos Verlinden;Bram Nauta;Anne-Johan Annema","doi":"10.1109/OJSSCS.2025.3636845","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3636845","url":null,"abstract":"This article describes a CMOS frequency reference system that achieves quartz-crystal-oscillator-rivaling frequency accuracy and power consumption across a temperature range of 228 °C, with low degradation over lifetime. This system uses only a batch calibration and a sample-specific single-temperature production-time calibration. The reference frequency is generated by a tunable RC-based oscillator (RCO) at relatively low power. The RCO’s significant process and temperature dependencies, and degradation over lifetime, are eliminated by periodically recalibrating it to a co-integrated inherently robust LC-oscillator (LCO). The resulting hybrid RC/LC CMOS frequency reference system combines the low-power properties of the RCO and the single-trim highly accurate and low-aging properties of an LCO. This article reviews circuit and system aspects of this frequency reference system, complemented with measurement results and insights for key devices and for many effects that limit system accuracy over wide temperature ranges and over lifetime.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"481-496"},"PeriodicalIF":3.2,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11268377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent Advances in Energy-Efficient and Temperature-Resilient Sensor Interfaces","authors":"Woojun Choi;Inhee Lee;Youngwoo Ji;Alexander Delke;Sining Pan;Zhong Tang;Youngcheol Chae","doi":"10.1109/OJSSCS.2025.3634970","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3634970","url":null,"abstract":"The rapid growth of power-constrained applications, including the Internet of Things (IoT) and wearables, demands sensor interfaces with high accuracy and reliability. A fundamental design challenge arises as their performance is severely limited by thermal drift within the analog front-end (AFE) and analog-to-digital converter (ADC) circuits. To address this, this article reviews two principal strategies: 1) the development of robust voltage and frequency reference circuits and 2) the implementation of on-chip temperature calibration. The review covers state-of-the-art temperature-compensated voltage references, such as subthreshold and BJT/MOS hybrid architectures, as well as stable frequency references based on LC and RC time constants. Furthermore, it examines advanced sensor interfaces that integrate on-chip temperature sensors for real-time error correction, featuring recent case studies on current sensor designs. These comprehensive advances are crucial for enabling reliable, energy-efficient sensor interfaces intended for precision-critical applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"456-469"},"PeriodicalIF":3.2,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11260455","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A PVT-Tolerant, Curvature-Compensated CMOS Bandgap-Based Current Reference With Single-Point Batch Trim","authors":"Ayman Sakr;Mohamed Atef Hassan;Jens Anders","doi":"10.1109/OJSSCS.2025.3633660","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3633660","url":null,"abstract":"Traditional bandgap-based current references display various limitations. This includes large temperature coefficients (TCs) across process corners, necessitating costly trimming cycles, and area inefficiency for low current values (<<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>A). This work addresses these shortcomings by generating a complementary-to-absolute-temperature (CTAT) current that reproduces the temperature dependence of the proportional-to-absolute-temperature (PTAT) current, including its curvature over process corners, eliminating multitemperature TC trimming while retaining a single-point room-temperature calibration to set the absolute current. The design provides this matching PTAT/CTAT feature by relying on the temperature-stable negative TC of the electron mobility to generate the CTAT current instead of the nonlinear and process-sensitive diode-based CTAT generation. Moreover, thanks to the mobility-based CTAT generation, high-resistivity undoped poly resistors with a strong negative TC can be used, enabling area-efficient CTAT current generation in the sub-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A to single-digit <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A range. To validate the proposed approach, we fabricated a prototype design in a 130-nm SOI CMOS technology, occupying an active area of only 0.016 mm2 and operating over a wide supply range from 1.6 to 3 V. Measurements from 10 chips yield a mean current of <inline-formula> <tex-math>$1.1~mu $ </tex-math></inline-formula>A (<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>/<inline-formula> <tex-math>$mu ~approx ~4.4$ </tex-math></inline-formula>%) close to the design target of <inline-formula> <tex-math>$1.2~mu $ </tex-math></inline-formula>A. Experimental results further demonstrate an average TC of 110 ppm/°C from <inline-formula> <tex-math>$0~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$100~^{circ }$ </tex-math></inline-formula>C without multitemperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"470-480"},"PeriodicalIF":3.2,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11251149","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Current-Steering 6-GHz Power Amplifier With Extensive Reconfigurability for Cryogenic Operation in 65 nm CMOS","authors":"Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3631573","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3631573","url":null,"abstract":"Emerging W<sc>ireless</small> sensor networks for deep space exploration demand highly reliable RF transmitters capable of operating in extreme environments, where temperatures can drop well below liquid nitrogen temperature. CMOS power amplifiers (PAs) for these systems must withstand wide temperature variations and preserve output power and linearity despite significant cryogenic shifts in MOSFET parameters such as threshold voltage and carrier mobility. Conventional process design kit (PDK) models, limited to–55 °C to 125 °C, exacerbate the challenge by offering insufficient support for cryogenic design and validation. This work introduces a high-efficiency current-steering CMOS PA designed for robust operation at cryogenic temperatures down to 4.2 K. The PA employs a reconfigurable output stage to compensate for temperature-induced device variations and uses current-steering device pairs to shape drain current at the output stage for enhancing efficiency and linearity. A 65-nm CMOS prototype achieves a peak drain efficiency (DE) of 42.8% and an OP1dB of 13.6 dBm at 6.3 GHz when cooled to 4.2 K. These results highlight the potential of highly configurable CMOS PAs for enabling energy-efficient wireless communication in space and other extreme cryogenic environments.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"497-510"},"PeriodicalIF":3.2,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11240125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 64-Element 28 GHz Digital Beamformer Based on Tileable Synchronized Distributed Beamforming Chiplets","authors":"Christine Weston;Rundao Lu;Zhengqi Xu;Hao Yu;Daniel Lambalot;Michael P. Flynn","doi":"10.1109/OJSSCS.2025.3625891","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3625891","url":null,"abstract":"A tileable 16-element, 4-beam, 28 GHz digital beamforming chiplet communicates over a power-efficient, low-latency Streaming-Advanced Interface Bus (AIB) data link to distribute digital beamforming processing across multiple chiplets. Spiral chiplet connectivity enables scaling to a large array size with a single beamforming chiplet design. The chiplet includes a 28 GHz frontend, analog-to-digital converters (ADCs), digital beamform processing and Streaming-AIB receive and transmit interfaces. A multichip digital phase-locked loop (PLL) ensures digital clock synchronization between chiplets. Scalability is demonstrated with a prototype 4-chiplet, 64-element module. Over-the-air tests confirm accurate 64-element beam patterns, a double-sideband (DSB) noise figure of 17 dB, a Streaming-AIB bit error rate (BER) of 3E-12, and a low power consumption of 23 mW per beam-channel.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"424-436"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dynamically Reconfigurable Power Management System With Self-Monitoring Capabilities for Energy-Efficient SoCs","authors":"Henrique Pocinho;Rodrigo Capeleiro;Tiago Moita;José Proença;Floriberto Lima;Marcelino B. Dos Santos;Fábio Passos","doi":"10.1109/OJSSCS.2025.3624690","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3624690","url":null,"abstract":"This article presents a dynamically reconfigurable power management unit (PMU) with self-monitoring capabilities, designed to enable ultralow power (ULP) operation. The proposed system consumes just <inline-formula> <tex-math>$1.68~{mu }$ </tex-math></inline-formula>W, which represents a 30% reduction in power consumption when compared to state-of-the-art implementations operating at 32 kHz. Fabricated in 22-nm FD-SOI technology, the proposed PMU leverages a novel real-time clock (RTC) architecture that provides performance and workload self-monitoring capabilities and also has the capability to change its operation modes automatically based on current workload. With the usage of such RTC, the PMU eliminates the need for external control units, complex state machines or processors, significantly reducing system complexity and silicon area. Since RTCs are already present in many systems and the proposed architecture only requires a 15% area increase for additional state-control registers, it makes it particularly well-suited for implantable, wearable or other Internet of Medical Things (IoMT) devices, where energy autonomy, system miniaturization, and safe long-term operation are essential.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"365-376"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218198","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems","authors":"Lukas Pfromm;Alish Kanani;Harsh Sharma;Janardhan Rao Doppa;Partha Pratim Pande;Umit Y. Ogras","doi":"10.1109/OJSSCS.2025.3626314","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3626314","url":null,"abstract":"Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework’s versatility, up to 340% accuracy improvement, and power/thermal analysis capability.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"410-423"},"PeriodicalIF":3.2,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218851","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}