IEEE Open Journal of the Solid-State Circuits Society最新文献_第4页

Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at K/Ka- and E/W-Band 在 K/Ka 和 E/W 波段使用晶格网络的超宽带 4 位分布式移相器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-09-02 DOI: 10.1109/OJSSCS.2024.3453777

Sungwon Kwon;Minjae Jung;Byung-Wook Min

{"title":"Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at K/Ka- and E/W-Band","authors":"Sungwon Kwon;Minjae Jung;Byung-Wook Min","doi":"10.1109/OJSSCS.2024.3453777","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3453777","url":null,"abstract":"In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.6pm 0$ </tex-math></inline-formula>\u0000.8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.9pm 1$ </tex-math></inline-formula>\u0000.1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"122-130"},"PeriodicalIF":0.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations 增强功率放大器中的射频指纹生成：不等间隔多音设计方法和注意事项

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-08-30 DOI: 10.1109/OJSSCS.2024.3451401

Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen

{"title":"Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations","authors":"Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2024.3451401","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3451401","url":null,"abstract":"The rapid growth of Internet of Things (IoT) devices and communication standards has led to an increasing demand for data security, particularly with limited hardware resources. In addition to conventional software-level data encryption, physical-layer security techniques, such as device-specific radio frequency fingerprints (RFFs), are emerging as promising solutions. This article first summarizes prior arts on timestamped RFFs generation and reconfigurable power amplifier (PA) designs. Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. Multiple 3-bit resistive digital-to-analog converters (RDACs) are applied to control body biasing units within the two-stage PA, facilitating the generation of massive and distinguishable RFFs. Subsequently, time-varying unequally spaced multitone (USMT) techniques are proposed to further elevate the count of available timestamped RFFs from 4096 to 16 384. The validation results of RFFs utilizing 64-QAM WiFi-6E advertising packets, employing time-varying USMT transmitted within the 5.39–5.41-GHz band, confirm the successful generation of 16 384 distinct RFF patterns. Moreover, the measurement results demonstrate that more than 11 504 RFFs among the generated patterns can be classified with an accuracy exceeding 99%.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"83-96"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10660491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142235709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Insights Into Architectural Spurs in High-Performance Fractional-N Frequency Synthesizers 深入了解高性能分数n频率合成器的架构马刺

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-08-26 DOI: 10.1109/OJSSCS.2024.3450410

Michael Peter Kennedy;Xu Lu;Xu Wang

引用次数: 0

A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking 通过参考电导跟踪进行漂移补偿的基于 PCM 的模拟内存计算读出方案

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-07-25 DOI: 10.1109/OJSSCS.2024.3432468

Alessio Antolini;Andrea Lico;Francesco Zavalloni;Eleonora Franchi Scarselli;Antonio Gnudi;Mattia Luigi Torres;Roberto Canegallo;Marco Pasotti

{"title":"A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking","authors":"Alessio Antolini;Andrea Lico;Francesco Zavalloni;Eleonora Franchi Scarselli;Antonio Gnudi;Mattia Luigi Torres;Roberto Canegallo;Marco Pasotti","doi":"10.1109/OJSSCS.2024.3432468","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3432468","url":null,"abstract":"This article presents a readout scheme for analog in-memory computing (AIMC) based on an embedded phase-change memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the phase-change memory (PCM) devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions and show that the mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-h bake at \u0000<inline-formula> <tex-math>$85~{^{circ }}$ </tex-math></inline-formula>\u0000C. Based on several MAC operations, the estimated \u0000<inline-formula> <tex-math>$512times 512$ </tex-math></inline-formula>\u0000 matrix-vector-multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"69-82"},"PeriodicalIF":0.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Speed Wireline Links—Part I: Modeling 高速有线链路--第一部分：建模

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-07-24 DOI: 10.1109/OJSSCS.2024.3433324

Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami

引用次数: 0

High-Speed Wireline Links—Part II: Optimization and Performance Assessment 高速有线链路--第二部分：优化和性能评估

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-07-01 DOI: 10.1109/OJSSCS.2024.3421868

Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami

引用次数: 0

A 0.69-mW Subsampling NB-IoT Receiver Employing a Linearized Q-Boosted LNA 采用线性化 Q 升压低噪声放大器的 0.69 毫瓦采样 NB-IoT 接收器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-06-19 DOI: 10.1109/OJSSCS.2024.3416893

Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier

引用次数: 0

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL A-102 dBm 灵敏度、集成 ADPLL 的多通道异频唤醒接收器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-04-10 DOI: 10.1109/OJSSCS.2024.3387388

Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers

引用次数: 0

IEEE Open Journal of the Solid-State Circuits Society IEEE 固态电路学会公开期刊

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-01-04 DOI: 10.1109/OJSSCS.2023.3346008

引用次数: 0

IEEE Open Journal of the Solid-State Circuits Society Information for Authors IEEE 固态电路学会公开期刊作者须知

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2023-12-22 DOI: 10.1109/OJSSCS.2023.3346150

引用次数: 0