深入了解高性能分数n频率合成器的架构马刺

Michael Peter Kennedy;Xu Lu;Xu Wang
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引用次数: 0

摘要

由于小数 N 频率合成器的输出频率不是其参考频率的整数倍,因此它本身就会产生脉冲。直到最近,人们似乎还能理解并控制分数脉冲。然而,随着人们对频率合成器的性能要求越来越高,新的脉冲产生机制和现象也不断被报道出来。因此,人们开始了紧张的研究工作,以了解造成这些问题的原因,并开发出缓解这些问题的方法。本文回顾了已知的情况,重点介绍了在理解和缓解技术方面的一些最新进展,并指出了数字密集型架构面临的新挑战。文章只关注架构中固有的(而不是由于耦合或封装问题造成的)、因此适合架构解决方案的刺激机制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Insights Into Architectural Spurs in High-Performance Fractional-N Frequency Synthesizers
A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.
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