Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan
{"title":"低压高精度开关电容δ - σ调制器的分析与设计","authors":"Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan","doi":"10.1109/OJSSCS.2024.3517600","DOIUrl":null,"url":null,"abstract":"Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"157-166"},"PeriodicalIF":3.2000,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10803003","citationCount":"0","resultStr":"{\"title\":\"Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator\",\"authors\":\"Weiqiang Chen;Lingxin Meng;Menglian Zhao;Zhichao Tan\",\"doi\":\"10.1109/OJSSCS.2024.3517600\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.\",\"PeriodicalId\":100633,\"journal\":{\"name\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"volume\":\"5 \",\"pages\":\"157-166\"},\"PeriodicalIF\":3.2000,\"publicationDate\":\"2024-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10803003\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10803003/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10803003/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator
Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency. This article includes the current development of low-voltage DSMs and the design challenges of low-voltage discrete-time (DT) DSMs. As a case study, a DT zoom DSM with a low-voltage capacitively biased floating inverter amplifier is presented with detailed design considerations. Fabricated in 55-nm CMOS under a 0.5-V supply, the prototype achieves 83.6-dB signal-to-noise-and-distortion ratio (SNDR) and 86.0-dB dynamic range while only consuming 664 nW at a signal bandwidth of 1 kHz. This achieves a state-of-the-art SNDR-based figure of merit of 175.4 dB among low-voltage switched-capacitor DSMs.