采用浮动环放大器和增益增强米勒负c的150毫秒/秒全动态sar辅助管道ADC

IF 3.2
Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn
{"title":"采用浮动环放大器和增益增强米勒负c的150毫秒/秒全动态sar辅助管道ADC","authors":"Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn","doi":"10.1109/OJSSCS.2024.3513255","DOIUrl":null,"url":null,"abstract":"This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"145-156"},"PeriodicalIF":3.2000,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10783016","citationCount":"0","resultStr":"{\"title\":\"A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C\",\"authors\":\"Seungheun Song;Taewook Kang;Seungjong Lee;Michael P. Flynn\",\"doi\":\"10.1109/OJSSCS.2024.3513255\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.\",\"PeriodicalId\":100633,\"journal\":{\"name\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"volume\":\"5 \",\"pages\":\"145-156\"},\"PeriodicalIF\":3.2000,\"publicationDate\":\"2024-12-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10783016\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10783016/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10783016/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文介绍了一种全动态sar辅助管道模数转换器(ADC),该转换器采用浮动环放大器(FLORA)和增益增强米勒负电容(Miller负c)。FLORA是一个完全动态和无偏置的环形放大器,由蓄水池电容器供电。自动归零和放大相位的不同电容优化了功耗和优势极位。此外,FLORA提高了速度,而不需要在每一级使用共模负载电容器,也不需要在输出端使用开关电容共模反馈电路。Miller负c通过减小与有限运算放大器增益和反馈因子乘积相关的增益误差,提高了闭环剩余放大器的精度。这种增益误差补偿方案不需要额外的电路或校正相位。它占地面积小,需要很少的额外功耗。本文分析了米勒负c放大器的稳定性、有效范围和沉降特性。采用28纳米CMOS工艺实现的原型ADC的SNDR和SFDR分别为67.9和84.3 dB,而在150 MS/s的1v电源下消耗1.72 mW。相应的Walden和Schreier SNDR值分别为5.7 fJ/转换步长和173 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C
This article introduces a fully dynamic SAR-assisted pipeline analog-to-digital converter (ADC) that uses a floating ring amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C). FLORA is a fully dynamic and bias-free ring amplifier powered by reservoir capacitors. Different reservoir capacitors for auto-zero and amplification phases optimize the power consumption and dominant pole locations. Furthermore, FLORA enhances speed without needing common-mode load capacitors in each stage and does not need a switched-capacitor common-mode feedback circuit at the output. The Miller negative-C improves the accuracy of the closed-loop residue amplifier by reducing the gain error related to the product of the finite operational amplifier gain and the feedback factor. This gain error compensation scheme eliminates the need for extra circuitry or correction phases. It occupies a small area and requires little additional power consumption. This article analyzes the stability, effective range, and settling behavior of an amplifier with Miller negative-C. The prototype ADC implemented in a 28-nm CMOS process achieves an SNDR and an SFDR of 67.9 and 84.3 dB, respectively, while consuming 1.72 mW at 150 MS/s from a 1-V supply. The corresponding Walden and Schreier SNDR figure of merits are 5.7 fJ/conversion-step and 173 dB, respectively.
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