Chip最新文献 - Book学术

Controllable floating gate memory performance through device structure design 通过器件结构设计实现可控浮栅存储器性能

IF 7.1

Chip Pub Date : 2025-05-20 DOI: 10.1016/j.chip.2025.100151

Ruitong Bie , Ce Li , Zirui Zhang , Tianze Yu , Dongliang Yang , Binghe Liu , Linfeng Sun

{"title":"Controllable floating gate memory performance through device structure design","authors":"Ruitong Bie , Ce Li , Zirui Zhang , Tianze Yu , Dongliang Yang , Binghe Liu , Linfeng Sun","doi":"10.1016/j.chip.2025.100151","DOIUrl":"10.1016/j.chip.2025.100151","url":null,"abstract":"<div><div>Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attributed to variations in material thickness or interface quality without a detailed exploration. Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory. Here, we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions. For the first time, the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated. Moreover, controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated. The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100151"},"PeriodicalIF":7.1,"publicationDate":"2025-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144890739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A C-band cryogenic gallium arsenide low-noise amplifier for quantum applications 用于量子应用的c波段低温砷化镓低噪声放大器

IF 7.1

Chip Pub Date : 2025-04-03 DOI: 10.1016/j.chip.2025.100146

Zechen Guo , Daxiong Sun , Peisheng Huang , Xuandong Sun , Yuefeng Yuan , Jiawei Zhang , Wenhui Huang , Yongqi Liang , Jiawei Qiu , Jiajian Zhang , Ji Chu , Weijie Guo , Ji Jiang , Jingjing Niu , Wenhui Ren , Ziyu Tao , Xiayu Linpeng , Youpeng Zhong , Dapeng Yu

{"title":"A C-band cryogenic gallium arsenide low-noise amplifier for quantum applications","authors":"Zechen Guo , Daxiong Sun , Peisheng Huang , Xuandong Sun , Yuefeng Yuan , Jiawei Zhang , Wenhui Huang , Yongqi Liang , Jiawei Qiu , Jiajian Zhang , Ji Chu , Weijie Guo , Ji Jiang , Jingjing Niu , Wenhui Ren , Ziyu Tao , Xiayu Linpeng , Youpeng Zhong , Dapeng Yu","doi":"10.1016/j.chip.2025.100146","DOIUrl":"10.1016/j.chip.2025.100146","url":null,"abstract":"<div><div>Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNAs) for qubit readout. Here we presented a C-band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on a 150 nm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance matching to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third stages enhances the overall stability. Moreover, the pHEMT self-bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only a single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a minimum noise temperature of 4 K and an average gain of 40 dB. We further benchmarked this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100146"},"PeriodicalIF":7.1,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb) 基于单层GeX2 （X = As, Sb）的N型和p型亚10nm高性能晶体管

Chip Pub Date : 2025-03-29 DOI: 10.1016/j.chip.2025.100144

Siyu Yang, Hao Shi, Yang Hu, Xinwei Guo, Xiaojia Yuan, Hengze Qu, Haibo Zeng, Shengli Zhang

{"title":"N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb)","authors":"Siyu Yang, Hao Shi, Yang Hu, Xinwei Guo, Xiaojia Yuan, Hengze Qu, Haibo Zeng, Shengli Zhang","doi":"10.1016/j.chip.2025.100144","DOIUrl":"10.1016/j.chip.2025.100144","url":null,"abstract":"<div><div>Exploring silicon alternatives for channel material is crucial for next-generation integrated circuits, two-dimensional (2D) materials are the most promising candidates due to their capability to suppress short-channel effects. In this study, we conducted simulations on the structural and electronic properties of 2D GeX<sub>2</sub> (X = As, Sb), as well as the ballistic transport characteristics of sub-10 nm n- and p-type 2D GeX<sub>2</sub> field effect transistors (FETs) based on first principles. The key metrics in terms of on-state current (<em>I</em><sub>on</sub>), delay time, and power consumption of n-type GeAs<sub>2</sub> and p-type GeSb<sub>2</sub> FETs can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices until the gate length (<em>L</em><sub>g</sub>) is shrunk to 5 nm. Specifically, the <em>I</em><sub>on</sub> of n-type GeAs<sub>2</sub> FET and p-type GeSb<sub>2</sub> FET reaches 2299 and 1480 μA/μm when <em>L</em><sub>g</sub> is 7 nm, surpassing InSe, MoS<sub>2</sub><sub>,</sub> and WSe<sub>2</sub> FETs. Our work highlights the potential of 2D GeX<sub>2</sub> in future nanoelectronics.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100144"},"PeriodicalIF":0.0,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144679711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-performance tensor computing unit for deep learning acceleration 用于深度学习加速的高性能张量计算单元

Chip Pub Date : 2025-03-28 DOI: 10.1016/j.chip.2025.100145

Qiang Zhou , Tieli Sun , Taoran Shen , York Xue

{"title":"A high-performance tensor computing unit for deep learning acceleration","authors":"Qiang Zhou , Tieli Sun , Taoran Shen , York Xue","doi":"10.1016/j.chip.2025.100145","DOIUrl":"10.1016/j.chip.2025.100145","url":null,"abstract":"<div><div>The increasing complexity of neural network applications has led to a demand for higher computational parallelism and more efficient synchronization in artificial intelligence (AI) chips. To achieve higher performance and lower power, a comprehensive and efficient approach is required to compile neural networks for implementation on dedicated hardware. Our first-generation deep learning accelerator, tensor computing unit, was presented with hardware and software solutions. It offered dedicated very long instruction words (VLIWs) instructions and multi-level repeatable direct memory access (DMA). The former lowers the instruction bandwidth requirement and makes it easier to parallelize the index and vector computations. The latter reduces the communication latency between the compute core and the asynchronous DMA, and also greatly alleviates the programming complexity. For operator implementation and optimization, the compiler-based data-flow generator and the instruction macro generator first produced a set of parameterized operators. Then, the tuner-configuration generator pruned the search space and the distributed tuner framework selected the best data-flow pattern and corresponding parameters. Our tensor computing unit supports all the convolution parameters with full-shape dimensions. It can readily select proper operators to achieve 96% of the chip peak performance under certain shapes and find the best performance implementation within limited power. The evaluation of a large number of convolution shapes on our tensor computing unit chip shows the generated operators significantly outperform the hand-written ones, achieving 9% higher normalized performance than CUDA according to the silicon data.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100145"},"PeriodicalIF":0.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Polarization reversal enhanced intelligent recognition in two-dimensional MoTe2/GeSe heterostructure 极化反转增强了二维MoTe2/GeSe异质结构的智能识别

Chip Pub Date : 2025-03-27 DOI: 10.1016/j.chip.2025.100143

Ling Bai , Ziting Yang , Jie Wen , Zifeng Mai , Bin Liu , Duanyang Liu , Penghong Ci , Liyuan Liu , Yiyang Xie , Ziqi Zhou , Yali Yu , Zhongming Wei

{"title":"Polarization reversal enhanced intelligent recognition in two-dimensional MoTe2/GeSe heterostructure","authors":"Ling Bai , Ziting Yang , Jie Wen , Zifeng Mai , Bin Liu , Duanyang Liu , Penghong Ci , Liyuan Liu , Yiyang Xie , Ziqi Zhou , Yali Yu , Zhongming Wei","doi":"10.1016/j.chip.2025.100143","DOIUrl":"10.1016/j.chip.2025.100143","url":null,"abstract":"<div><div>Wide-spectral and polarization-sensitive photodetectors are vital for applications in imaging, communication, and intelligent sensing. Although two-dimensional (2D) materials have shown great promise in enhancing the performance of these devices, conventional methods for spectral discrimination often rely on complex designs, such as external filters or multisensor systems, increasing system cost and complexity. Developing simplified devices that integrate spectral and polarization detection remains a key challenge. Here, we demonstrated a 2D MoTe<sub>2</sub>/GeSe-based photodetector with wide-spectral photoresponse (400 to 1064 nm) and polarization sensitivity, achieving a responsivity of 1.35 A W<sup>−1</sup> and a polarization ratio of 2.23 under 808 nm illumination. The device exhibited a unique 90° polarization reversal between green (532 nm) and red (808 nm), providing a novel mechanism for spectral discrimination. First-principles calculations reveal the polarization reversal phenomenon based on the heterostructure's optical anisotropy. Furthermore, integration with a convolutional neural network enables intelligent traffic signal recognition using polarization-sensitive images. This work highlights the potential of MoTe<sub>2</sub>/GeSe heterostructures for next-generation photodetectors, offering compact, multifunctional solutions with integrated spectral and polarization discrimination capabilities.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100143"},"PeriodicalIF":0.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144298768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Root cause of read after delay in ferroelectric memories 铁电存储器延迟后读取的根本原因

Chip Pub Date : 2025-03-16 DOI: 10.1016/j.chip.2025.100139

Diqing Su , Shaorui Li , Xiao Wang , Yannan Xu , Qingting Ding , Heng Zhang , Hangbing Lyu

{"title":"Root cause of read after delay in ferroelectric memories","authors":"Diqing Su , Shaorui Li , Xiao Wang , Yannan Xu , Qingting Ding , Heng Zhang , Hangbing Lyu","doi":"10.1016/j.chip.2025.100139","DOIUrl":"10.1016/j.chip.2025.100139","url":null,"abstract":"<div><div>Accelerated margin loss during read after delay (RAD) is a newly discovered reliability concern in HfO<sub>2</sub>-based ferroelectric random access memories (FeRAMs), which significantly impacts the lifetime of the memory device. Unlike conventional fatigue effect, this issue is closely linked to the coercive field (<span><math><mrow><msub><mi>E</mi><mi>c</mi></msub></mrow></math></span>) shift, or imprint, during bipolar electrical field cycling at intermediate frequency. The precise cause of imprint during RAD, however, remains elusive. To investigate, we employed customized electrical testing to examine the charge transfer behavior in static imprint (SI) and continuous read/write (CRW) scenarios, which can be viewed as RAD performed at minimum and maximum frequencies. Our findings reveal that interfacial charge injection is the primary mechanism for imprint in SI, while bulk charge drives the imprint in asymmetric CRW. Further exploration with a SPICE-based charge transfer model suggests that RAD-related imprint is the result of bulk charge migration, driven by the periodically restored depolarization field after read/write-back operation. Experimental verification supports this theory, highlighting the importance of interface engineering to enhance bound charge screening and element doping to elevate the migration barrier for bulk charges in addressing the RAD problem.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100139"},"PeriodicalIF":0.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144306710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An electrostatic micro-electromechanical systems micromirror with low-torsional stress supported by three-asymptote beam 一种由三渐近线梁支撑的静电微机电系统低扭转应力微镜

Chip Pub Date : 2025-03-16 DOI: 10.1016/j.chip.2025.100138

Xiao-Yong Fang , Ang Li , Er-Qi Tu, Bo Peng, Zhi-Ran Yi, Wen-Ming Zhang

{"title":"An electrostatic micro-electromechanical systems micromirror with low-torsional stress supported by three-asymptote beam","authors":"Xiao-Yong Fang , Ang Li , Er-Qi Tu, Bo Peng, Zhi-Ran Yi, Wen-Ming Zhang","doi":"10.1016/j.chip.2025.100138","DOIUrl":"10.1016/j.chip.2025.100138","url":null,"abstract":"<div><div>Micro-electromechanical systems (MEMS) micromirrors are preferred actuators in the field of light beam steering. Electrostatic micromirrors have gained vital attention due to their simple and compact structure. Among performance characteristics, the large field of view (FOV) and high structural reliability are key research hotspots. This work introduced a novel design of a three-asymptote support beam to improve the structural reliability, which is defined as a function with a shape coefficient, A. Simulation results reveal that the three-asymptote beam can reduce the chamfer stress from 690 MPa to 280 MPa compared with the conventional straight beam. Additionally, the resonant frequency of the micromirror can be adjusted via the shape coefficient. The micromirror prototype was fabricated using silicon-on-insulator-based micromachining and double-sided lithography technology. The vertically asymmetric electrostatic actuator comprises movable combs in the device layer and fixed combs in the handle layer. Furthermore, the performance of the prototype was tested in both static and resonant modes. The maximum static mechanical angle is 4.3° with a direct current voltage of 60 V, and the maximum angle is 3.1° at 445 Hz with a peak-to-peak voltage of 20 V in resonant mode.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100138"},"PeriodicalIF":0.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

All-optical Fourier neural network using partially coherent light 采用部分相干光的全光傅立叶神经网络

Chip Pub Date : 2025-03-16 DOI: 10.1016/j.chip.2025.100140

Jianwei Qin , Yanbing Liu , Yan Liu , Xun Liu , Wei Li , Fangwei Ye

{"title":"All-optical Fourier neural network using partially coherent light","authors":"Jianwei Qin , Yanbing Liu , Yan Liu , Xun Liu , Wei Li , Fangwei Ye","doi":"10.1016/j.chip.2025.100140","DOIUrl":"10.1016/j.chip.2025.100140","url":null,"abstract":"<div><div>Optical neural networks present distinct advantages over traditional electrical counterparts, such as accelerated data processing and reduced energy consumption. While coherent light is conventionally used in optical neural networks, our study proposed harnessing spatially incoherent light in all-optical Fourier neural networks. Contrary to natural predictions of declining target recognition accuracy with increased incoherence, our experimental results demonstrated a surprising outcome: improved accuracy with incoherent light. We attribute this enhancement to spatially incoherent light's ability to alleviate experimental errors like diffraction rings and laser speckle. Our experiments introduced controllable spatial incoherence by passing monochromatic light through a spatial light modulator featuring a dynamically changing random phase array. These findings underscore partially coherent light's potential to optimize optical neural networks, delivering dependable and efficient solutions for applications demanding consistent accuracy and robustness across diverse conditions, including on-chip optical computing, photonic interconnects, and reconfigurable optical processors.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100140"},"PeriodicalIF":0.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144569814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On-chip differential mode group delay manipulation based on 3D waveguides 基于三维波导的片上差分模群延迟处理

Chip Pub Date : 2025-03-08 DOI: 10.1016/j.chip.2025.100137

Xiaofeng Liu , Quandong Huang , Jiaqi Ran , Jiali Zhang , Ou Xu , Di Peng , Yuwen Qin

{"title":"On-chip differential mode group delay manipulation based on 3D waveguides","authors":"Xiaofeng Liu , Quandong Huang , Jiaqi Ran , Jiali Zhang , Ou Xu , Di Peng , Yuwen Qin","doi":"10.1016/j.chip.2025.100137","DOIUrl":"10.1016/j.chip.2025.100137","url":null,"abstract":"<div><div>Mode-division multiplexing based on few-mode optical fiber is a promising technology to increase the transmission capacity of optical communication systems, where multi-input multi-output (MIMO) digital signal processing (DSP) is employed to (de)multiplex the signals from different mode channels. Since the group velocity of each mode is different, the signals are separated in the time domain when they reach the receivers. Therefore, it is necessary to compensate for the mode-group-velocity delay of the interval modes to reduce the complexity of the MIMO-DSP algorithm. In this work, we demonstrated an on-chip differential-mode group delay (DMGD) manipulating device based on 3D multilayer cladding waveguides. The proposed device supports compensating the DMGD of about 10.0 ps/m with a device formed with a low refractive index difference. In the meanwhile, the value of DMGD can be greatly improved to be 1878.6 ps/m by forming the device with high refractive index difference material such as thin-film lithium niobate with silicon dioxide cladding. The proposed device provides a feasible design for on-chip DMGD manipulation, which can find various applications in the mode division multiplexing system.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100137"},"PeriodicalIF":0.0,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-efficiency modeling method for analog integrated circuits 模拟集成电路的一种高效建模方法

Chip Pub Date : 2025-03-07 DOI: 10.1016/j.chip.2025.100135

Dongdong Chen , Yunqi Yang , Xianglong Wang , Di Li , Guoqing Xin , Yintang Yang

{"title":"A high-efficiency modeling method for analog integrated circuits","authors":"Dongdong Chen , Yunqi Yang , Xianglong Wang , Di Li , Guoqing Xin , Yintang Yang","doi":"10.1016/j.chip.2025.100135","DOIUrl":"10.1016/j.chip.2025.100135","url":null,"abstract":"<div><div>Integrated circuits (ICs) are the foundation of information technology development. The optimal design scheme of an analog IC is determined by iteratively running the simulation software and comparing the performance metrics. However, the simulation software of an analog IC is time-consuming, which leads to the low design efficiency. Due to the nonideal factors in analog ICs, the nonlinear relationship between design parameters and performance metrics cannot be well described by the deduced approximation equations. Inspired by the image and semantic recognition, a universal high-efficiency modeling method for analog ICs based on convolutional neural network (CNN) was proposed in the current work, named as CNN-IC. The sparse topology mapping method was proposed to map the design parameters into a sparse matrix, which includes the spatial and transistor characteristics of analog IC. The CNN model with three convolutional kernels was constructed to extract “transistor-circuit module-integrate circuit” features level by level, which can replace the simulation software to effectively improve the training efficiency and accuracy. Two typical analog ICs were selected to verify the effectiveness of the CNN-IC model. The results show that the accuracy of the CNN-IC model could reach over 99% and that its convergence rate was the fastest compared with the machine learning models in the state of the art.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100135"},"PeriodicalIF":0.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144338906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0