Chip最新文献

{"title":"N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb)","authors":"Siyu Yang,&nbsp;Hao Shi,&nbsp;Yang Hu,&nbsp;Xinwei Guo,&nbsp;Xiaojia Yuan,&nbsp;Hengze Qu,&nbsp;Haibo Zeng,&nbsp;Shengli Zhang","doi":"10.1016/j.chip.2025.100144","DOIUrl":"10.1016/j.chip.2025.100144","url":null,"abstract":"<div><div>Exploring silicon alternatives for channel material is crucial for next-generation integrated circuits, two-dimensional (2D) materials are the most promising candidates due to their capability to suppress short-channel effects. In this study, we conducted simulations on the structural and electronic properties of 2D GeX₂ (X = As, Sb), as well as the ballistic transport characteristics of sub-10 nm n- and p-type 2D GeX₂ field effect transistors (FETs) based on first principles. The key metrics in terms of on-state current (<em>I</em>_on), delay time, and power consumption of n-type GeAs₂ and p-type GeSb₂ FETs can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices until the gate length (<em>L</em>_g) is shrunk to 5 nm. Specifically, the <em>I</em>_on of n-type GeAs₂ FET and p-type GeSb₂ FET reaches 2299 and 1480 μA/μm when <em>L</em>_g is 7 nm, surpassing InSe, MoS₂_, and WSe₂ FETs. Our work highlights the potential of 2D GeX₂ in future nanoelectronics.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100144"},"PeriodicalIF":0.0,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144679711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high-performance tensor computing unit for deep learning acceleration","authors":"Qiang Zhou ,&nbsp;Tieli Sun ,&nbsp;Taoran Shen ,&nbsp;York Xue","doi":"10.1016/j.chip.2025.100145","DOIUrl":"10.1016/j.chip.2025.100145","url":null,"abstract":"<div><div>The increasing complexity of neural network applications has led to a demand for higher computational parallelism and more efficient synchronization in artificial intelligence (AI) chips. To achieve higher performance and lower power, a comprehensive and efficient approach is required to compile neural networks for implementation on dedicated hardware. Our first-generation deep learning accelerator, tensor computing unit, was presented with hardware and software solutions. It offered dedicated very long instruction words (VLIWs) instructions and multi-level repeatable direct memory access (DMA). The former lowers the instruction bandwidth requirement and makes it easier to parallelize the index and vector computations. The latter reduces the communication latency between the compute core and the asynchronous DMA, and also greatly alleviates the programming complexity. For operator implementation and optimization, the compiler-based data-flow generator and the instruction macro generator first produced a set of parameterized operators. Then, the tuner-configuration generator pruned the search space and the distributed tuner framework selected the best data-flow pattern and corresponding parameters. Our tensor computing unit supports all the convolution parameters with full-shape dimensions. It can readily select proper operators to achieve 96% of the chip peak performance under certain shapes and find the best performance implementation within limited power. The evaluation of a large number of convolution shapes on our tensor computing unit chip shows the generated operators significantly outperform the hand-written ones, achieving 9% higher normalized performance than CUDA according to the silicon data.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100145"},"PeriodicalIF":0.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polarization reversal enhanced intelligent recognition in two-dimensional MoTe2/GeSe heterostructure","authors":"Ling Bai ,&nbsp;Ziting Yang ,&nbsp;Jie Wen ,&nbsp;Zifeng Mai ,&nbsp;Bin Liu ,&nbsp;Duanyang Liu ,&nbsp;Penghong Ci ,&nbsp;Liyuan Liu ,&nbsp;Yiyang Xie ,&nbsp;Ziqi Zhou ,&nbsp;Yali Yu ,&nbsp;Zhongming Wei","doi":"10.1016/j.chip.2025.100143","DOIUrl":"10.1016/j.chip.2025.100143","url":null,"abstract":"<div><div>Wide-spectral and polarization-sensitive photodetectors are vital for applications in imaging, communication, and intelligent sensing. Although two-dimensional (2D) materials have shown great promise in enhancing the performance of these devices, conventional methods for spectral discrimination often rely on complex designs, such as external filters or multisensor systems, increasing system cost and complexity. Developing simplified devices that integrate spectral and polarization detection remains a key challenge. Here, we demonstrated a 2D MoTe₂/GeSe-based photodetector with wide-spectral photoresponse (400 to 1064 nm) and polarization sensitivity, achieving a responsivity of 1.35 A W⁻¹ and a polarization ratio of 2.23 under 808 nm illumination. The device exhibited a unique 90° polarization reversal between green (532 nm) and red (808 nm), providing a novel mechanism for spectral discrimination. First-principles calculations reveal the polarization reversal phenomenon based on the heterostructure's optical anisotropy. Furthermore, integration with a convolutional neural network enables intelligent traffic signal recognition using polarization-sensitive images. This work highlights the potential of MoTe₂/GeSe heterostructures for next-generation photodetectors, offering compact, multifunctional solutions with integrated spectral and polarization discrimination capabilities.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100143"},"PeriodicalIF":0.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144298768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Root cause of read after delay in ferroelectric memories","authors":"Diqing Su ,&nbsp;Shaorui Li ,&nbsp;Xiao Wang ,&nbsp;Yannan Xu ,&nbsp;Qingting Ding ,&nbsp;Heng Zhang ,&nbsp;Hangbing Lyu","doi":"10.1016/j.chip.2025.100139","DOIUrl":"10.1016/j.chip.2025.100139","url":null,"abstract":"<div><div>Accelerated margin loss during read after delay (RAD) is a newly discovered reliability concern in HfO₂-based ferroelectric random access memories (FeRAMs), which significantly impacts the lifetime of the memory device. Unlike conventional fatigue effect, this issue is closely linked to the coercive field (<span><math><mrow><msub><mi>E</mi><mi>c</mi></msub></mrow></math></span>) shift, or imprint, during bipolar electrical field cycling at intermediate frequency. The precise cause of imprint during RAD, however, remains elusive. To investigate, we employed customized electrical testing to examine the charge transfer behavior in static imprint (SI) and continuous read/write (CRW) scenarios, which can be viewed as RAD performed at minimum and maximum frequencies. Our findings reveal that interfacial charge injection is the primary mechanism for imprint in SI, while bulk charge drives the imprint in asymmetric CRW. Further exploration with a SPICE-based charge transfer model suggests that RAD-related imprint is the result of bulk charge migration, driven by the periodically restored depolarization field after read/write-back operation. Experimental verification supports this theory, highlighting the importance of interface engineering to enhance bound charge screening and element doping to elevate the migration barrier for bulk charges in addressing the RAD problem.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100139"},"PeriodicalIF":0.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144306710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An electrostatic micro-electromechanical systems micromirror with low-torsional stress supported by three-asymptote beam","authors":"Xiao-Yong Fang ,&nbsp;Ang Li ,&nbsp;Er-Qi Tu,&nbsp;Bo Peng,&nbsp;Zhi-Ran Yi,&nbsp;Wen-Ming Zhang","doi":"10.1016/j.chip.2025.100138","DOIUrl":"10.1016/j.chip.2025.100138","url":null,"abstract":"<div><div>Micro-electromechanical systems (MEMS) micromirrors are preferred actuators in the field of light beam steering. Electrostatic micromirrors have gained vital attention due to their simple and compact structure. Among performance characteristics, the large field of view (FOV) and high structural reliability are key research hotspots. This work introduced a novel design of a three-asymptote support beam to improve the structural reliability, which is defined as a function with a shape coefficient, A. Simulation results reveal that the three-asymptote beam can reduce the chamfer stress from 690 MPa to 280 MPa compared with the conventional straight beam. Additionally, the resonant frequency of the micromirror can be adjusted via the shape coefficient. The micromirror prototype was fabricated using silicon-on-insulator-based micromachining and double-sided lithography technology. The vertically asymmetric electrostatic actuator comprises movable combs in the device layer and fixed combs in the handle layer. Furthermore, the performance of the prototype was tested in both static and resonant modes. The maximum static mechanical angle is 4.3° with a direct current voltage of 60 V, and the maximum angle is 3.1° at 445 Hz with a peak-to-peak voltage of 20 V in resonant mode.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100138"},"PeriodicalIF":0.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"All-optical Fourier neural network using partially coherent light","authors":"Jianwei Qin ,&nbsp;Yanbing Liu ,&nbsp;Yan Liu ,&nbsp;Xun Liu ,&nbsp;Wei Li ,&nbsp;Fangwei Ye","doi":"10.1016/j.chip.2025.100140","DOIUrl":"10.1016/j.chip.2025.100140","url":null,"abstract":"<div><div>Optical neural networks present distinct advantages over traditional electrical counterparts, such as accelerated data processing and reduced energy consumption. While coherent light is conventionally used in optical neural networks, our study proposed harnessing spatially incoherent light in all-optical Fourier neural networks. Contrary to natural predictions of declining target recognition accuracy with increased incoherence, our experimental results demonstrated a surprising outcome: improved accuracy with incoherent light. We attribute this enhancement to spatially incoherent light's ability to alleviate experimental errors like diffraction rings and laser speckle. Our experiments introduced controllable spatial incoherence by passing monochromatic light through a spatial light modulator featuring a dynamically changing random phase array. These findings underscore partially coherent light's potential to optimize optical neural networks, delivering dependable and efficient solutions for applications demanding consistent accuracy and robustness across diverse conditions, including on-chip optical computing, photonic interconnects, and reconfigurable optical processors.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100140"},"PeriodicalIF":0.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144569814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-chip differential mode group delay manipulation based on 3D waveguides","authors":"Xiaofeng Liu ,&nbsp;Quandong Huang ,&nbsp;Jiaqi Ran ,&nbsp;Jiali Zhang ,&nbsp;Ou Xu ,&nbsp;Di Peng ,&nbsp;Yuwen Qin","doi":"10.1016/j.chip.2025.100137","DOIUrl":"10.1016/j.chip.2025.100137","url":null,"abstract":"<div><div>Mode-division multiplexing based on few-mode optical fiber is a promising technology to increase the transmission capacity of optical communication systems, where multi-input multi-output (MIMO) digital signal processing (DSP) is employed to (de)multiplex the signals from different mode channels. Since the group velocity of each mode is different, the signals are separated in the time domain when they reach the receivers. Therefore, it is necessary to compensate for the mode-group-velocity delay of the interval modes to reduce the complexity of the MIMO-DSP algorithm. In this work, we demonstrated an on-chip differential-mode group delay (DMGD) manipulating device based on 3D multilayer cladding waveguides. The proposed device supports compensating the DMGD of about 10.0 ps/m with a device formed with a low refractive index difference. In the meanwhile, the value of DMGD can be greatly improved to be 1878.6 ps/m by forming the device with high refractive index difference material such as thin-film lithium niobate with silicon dioxide cladding. The proposed device provides a feasible design for on-chip DMGD manipulation, which can find various applications in the mode division multiplexing system.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100137"},"PeriodicalIF":0.0,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high-efficiency modeling method for analog integrated circuits","authors":"Dongdong Chen ,&nbsp;Yunqi Yang ,&nbsp;Xianglong Wang ,&nbsp;Di Li ,&nbsp;Guoqing Xin ,&nbsp;Yintang Yang","doi":"10.1016/j.chip.2025.100135","DOIUrl":"10.1016/j.chip.2025.100135","url":null,"abstract":"<div><div>Integrated circuits (ICs) are the foundation of information technology development. The optimal design scheme of an analog IC is determined by iteratively running the simulation software and comparing the performance metrics. However, the simulation software of an analog IC is time-consuming, which leads to the low design efficiency. Due to the nonideal factors in analog ICs, the nonlinear relationship between design parameters and performance metrics cannot be well described by the deduced approximation equations. Inspired by the image and semantic recognition, a universal high-efficiency modeling method for analog ICs based on convolutional neural network (CNN) was proposed in the current work, named as CNN-IC. The sparse topology mapping method was proposed to map the design parameters into a sparse matrix, which includes the spatial and transistor characteristics of analog IC. The CNN model with three convolutional kernels was constructed to extract “transistor-circuit module-integrate circuit” features level by level, which can replace the simulation software to effectively improve the training efficiency and accuracy. Two typical analog ICs were selected to verify the effectiveness of the CNN-IC model. The results show that the accuracy of the CNN-IC model could reach over 99% and that its convergence rate was the fastest compared with the machine learning models in the state of the art.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100135"},"PeriodicalIF":0.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144338906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tunable optoelectronic memristor based on MoS2/BaTiO3 for neuromorphic vision","authors":"Ziliang Fang ,&nbsp;Bingyu Chen ,&nbsp;Rui Rong ,&nbsp;Hanrong Xie ,&nbsp;Manyan Xie ,&nbsp;Haoran Guo ,&nbsp;Yang Li ,&nbsp;Fangheng Fu ,&nbsp;Xu Ouyang ,&nbsp;Yuming Wei ,&nbsp;Gangding Peng ,&nbsp;Tiefeng Yang ,&nbsp;Huihui Lu ,&nbsp;Heyuan Guan","doi":"10.1016/j.chip.2025.100136","DOIUrl":"10.1016/j.chip.2025.100136","url":null,"abstract":"<div><div>Human vision–inspired neuromorphic devices have integrated architectures that combine sensing, computing, and storage functions, which can fundamentally avoid the energy waste caused by frequent data movement in the currently widely used von Neumann architecture, and have crucial application potential in advanced artificial intelligence chips that pursue low power consumption and low latency. However, previously reported visual neuromorphic devices either suffer complex floating gate, vertically stacked multilayer structures, or necessitate separated optical-sensing and synaptic units, realizing highly compact, non-volatile optoelectronic response and continuously tunable conductivity within a sententious architecture remains a significant challenge. Here, we presented a low-cost exfoliation and transfer method combined with spin-coating to fabricate molybdenum disulfide (MoS₂)/barium titanate (BaTiO₃) heterostructured optoelectronic devices. Based on the ferroelectricity of BaTiO₃ and the charge transport characteristics of MoS₂, the hysteresis of ferroelectric polarization upon both electric and optical stimulation is successfully endowed with reliable resistance state switching abilities, showing the advantages of low bias voltage operation (±2 V) and distinct 16 conductance states under light pulse irradiation. Besides, the MoS₂/BaTiO₃ device can be further used to emulate biological synaptic behavior and accomplish the transition from short-term memory (STM) to long-term memory (LTM). Notably, leveraging the dual characteristics of imaging and neuromorphic behavior, we constructed a multi-layer perceptron network integrating visual perception and image recognition, showing an accuracy of 97.6% in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. This work introduced a simple MoS₂/BaTiO₃ heterojunction architecture device, offering integrated perception, storage, and computing capabilities, providing a new possibility for future compact neuromorphic computing devices.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100136"},"PeriodicalIF":0.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144261296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SOT-MRAM-based true in-memory computing architecture for approximate multiplication","authors":"Min Song ,&nbsp;Qilong Tang ,&nbsp;Xintong Ouyang ,&nbsp;Wei Duan ,&nbsp;Yan Xu ,&nbsp;Shuai Zhang ,&nbsp;Long You","doi":"10.1016/j.chip.2025.100134","DOIUrl":"10.1016/j.chip.2025.100134","url":null,"abstract":"<div><div>The in-memory computing (IMC) paradigm emerges as an effective solution to break the bottlenecks of conventional von Neumann architecture. In the current work, an approximate multiplier in spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based true IMC (STIMC) architecture was presented, where computations were performed natively within the cell array instead of in peripheral circuits. Firstly, basic Boolean logic operations were realized by utilizing the feature of unipolar SOT device. Two majority gate-based imprecise compressors and an ultra-efficient approximate multiplier were then built to reduce the energy and latency. An optimized data mapping strategy facilitating bit-serial operations with an extensive degree of parallelism was also adopted. Finally, the performance enhancements by performing our approximate multiplier in image smoothing were demonstrated. Detailed simulation results show that the proposed 8 × 8 approximate multiplier could reduce the energy and latency at least by 74.2% and 44.4% compared with the existing designs. Moreover, the scheme could achieve improved peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM), ensuring high-quality image processing outcomes.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100134"},"PeriodicalIF":0.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}