Chip最新文献 - Book学术

A high-performance tensor computing unit for deep learning acceleration 用于深度学习加速的高性能张量计算单元

Chip Pub Date : 2025-03-28 DOI: 10.1016/j.chip.2025.100145

Qiang Zhou , Tieli Sun , Taoran Shen , York Xue

{"title":"A high-performance tensor computing unit for deep learning acceleration","authors":"Qiang Zhou , Tieli Sun , Taoran Shen , York Xue","doi":"10.1016/j.chip.2025.100145","DOIUrl":"10.1016/j.chip.2025.100145","url":null,"abstract":"<div><div>The increasing complexity of neural network applications has led to a demand for higher computational parallelism and more efficient synchronization in artificial intelligence (AI) chips. To achieve higher performance and lower power, a comprehensive and efficient approach is required to compile neural networks for implementation on dedicated hardware. Our first-generation deep learning accelerator, tensor computing unit, was presented with hardware and software solutions. It offered dedicated very long instruction words (VLIWs) instructions and multi-level repeatable direct memory access (DMA). The former lowers the instruction bandwidth requirement and makes it easier to parallelize the index and vector computations. The latter reduces the communication latency between the compute core and the asynchronous DMA, and also greatly alleviates the programming complexity. For operator implementation and optimization, the compiler-based data-flow generator and the instruction macro generator first produced a set of parameterized operators. Then, the tuner-configuration generator pruned the search space and the distributed tuner framework selected the best data-flow pattern and corresponding parameters. Our tensor computing unit supports all the convolution parameters with full-shape dimensions. It can readily select proper operators to achieve 96% of the chip peak performance under certain shapes and find the best performance implementation within limited power. The evaluation of a large number of convolution shapes on our tensor computing unit chip shows the generated operators significantly outperform the hand-written ones, achieving 9% higher normalized performance than CUDA according to the silicon data.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100145"},"PeriodicalIF":0.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SOT-MRAM-based true in-memory computing architecture for approximate multiplication 基于sot - mram的真正内存计算架构，用于近似乘法

Chip Pub Date : 2025-03-05 DOI: 10.1016/j.chip.2025.100134

Min Song , Qilong Tang , Xintong Ouyang , Wei Duan , Yan Xu , Shuai Zhang , Long You

{"title":"SOT-MRAM-based true in-memory computing architecture for approximate multiplication","authors":"Min Song , Qilong Tang , Xintong Ouyang , Wei Duan , Yan Xu , Shuai Zhang , Long You","doi":"10.1016/j.chip.2025.100134","DOIUrl":"10.1016/j.chip.2025.100134","url":null,"abstract":"<div><div>The in-memory computing (IMC) paradigm emerges as an effective solution to break the bottlenecks of conventional von Neumann architecture. In the current work, an approximate multiplier in spin-orbit torque magnetoresistive random access memory (SOT-MRAM) based true IMC (STIMC) architecture was presented, where computations were performed natively within the cell array instead of in peripheral circuits. Firstly, basic Boolean logic operations were realized by utilizing the feature of unipolar SOT device. Two majority gate-based imprecise compressors and an ultra-efficient approximate multiplier were then built to reduce the energy and latency. An optimized data mapping strategy facilitating bit-serial operations with an extensive degree of parallelism was also adopted. Finally, the performance enhancements by performing our approximate multiplier in image smoothing were demonstrated. Detailed simulation results show that the proposed 8 × 8 approximate multiplier could reduce the energy and latency at least by 74.2% and 44.4% compared with the existing designs. Moreover, the scheme could achieve improved peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM), ensuring high-quality image processing outcomes.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100134"},"PeriodicalIF":0.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Corrigendum to “Wang, Z. et al. Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing” Chip 2 (2023) 100044 范德华铁电晶体管：用于高精度神经形态计算的全方位人工突触 "的更正，Chip 2 (2023) 100044

Chip Pub Date : 2025-03-01 DOI: 10.1016/j.chip.2024.100100

Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun

引用次数: 0

Characterizing the spatial potential of an ion trap chip 表征离子阱芯片的空间电位

Chip Pub Date : 2025-03-01 DOI: 10.1016/j.chip.2024.100126

Qingqing Qin , Ting Chen , Xinfang Zhang , Baoquan Ou , Jie Zhang , Chunwang Wu , Yi Xie , Wei Wu , Pingxing Chen

{"title":"Characterizing the spatial potential of an ion trap chip","authors":"Qingqing Qin , Ting Chen , Xinfang Zhang , Baoquan Ou , Jie Zhang , Chunwang Wu , Yi Xie , Wei Wu , Pingxing Chen","doi":"10.1016/j.chip.2024.100126","DOIUrl":"10.1016/j.chip.2024.100126","url":null,"abstract":"<div><div>The accurate characterization of the spatial electric field generated by electrodes in a surface electrode trap is of paramount importance. In this pursuit, we have identified a simple yet highly precise parametric expression to describe the spatial field of a rectangular-shaped electrode. Leveraging this expression, we introduced an optimization method designed to accurately characterize the axial electric field intensity produced by the powered electrode and the stray field. Distinct from the existing methods, our approach integrates a diverse array of experimental data, including the equilibrium positions of ions in a linear string, the equilibrium positions of single trapped ions, and trap frequencies, to effectively reduce the systematic errors. This approach provides considerable flexibility in voltage settings for data acquisition, making it especially advantageous for surface electrode traps where the trapping height of ion probes may vary with casual voltage settings. In our experimental demonstration, we successfully minimized the discrepancy between observations and model predictions to a remarkable degree. The relative errors of secular frequencies were contained within ±0.5%, and the positional error of ions was constrained to less than 1.2 μm, which surpasses the performance of current methodologies.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 1","pages":"Article 100126"},"PeriodicalIF":0.0,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143636751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Complex-Amplitude-Modulated Meta-Device for Optical Image Processing 用于光学图像处理的复调幅元器件

Chip Pub Date : 2025-02-14 DOI: 10.1016/j.chip.2025.100132

Xincheng Jiang , Peicheng Lin , Yeang Zhang , Ting Xu , Yan-qing Lu , Jun-long Kou

引用次数: 0

Advances in piezotronics and piezo-phototronics of two-dimensional semiconductor materials 二维半导体材料的压电电子学和压电光电子学研究进展

Chip Pub Date : 2025-01-30 DOI: 10.1016/j.chip.2025.100131

Yitong Wang , Fangpei Li , Wenbo Peng , Yongning He

{"title":"Advances in piezotronics and piezo-phototronics of two-dimensional semiconductor materials","authors":"Yitong Wang , Fangpei Li , Wenbo Peng , Yongning He","doi":"10.1016/j.chip.2025.100131","DOIUrl":"10.1016/j.chip.2025.100131","url":null,"abstract":"<div><div>High-performance electronics and optoelectronics play vital roles in modern society, as they are the fundamental building blocks of functional devices and systems. Two-dimensional semiconductor materials (2D-SCMs) are potential candidates for high-performance electronics and optoelectronics due to their excellent physical, chemical, electrical, and photonic properties. Owing to their special crystalline structure, they also present unique piezoelectricity, which opens a new door to the innovative fields of piezotronics and piezo-phototronics. Piezotronics and piezo-phototronics utilize the piezoelectric polarization charges produced when the 2D-SCMs undergo externally applied strains/stresses to modulate the performance of 2D-SCMs-based electronics and optoelectronics. In this review, firstly, the growth methods and piezoelectric properties of 2D-SCMs are stated, and the mechanisms of piezotronics and piezo-phototronics are also introduced. Afterwards, the recent progress of piezotronics and piezo-phototronics in high-performance 2D-SMCs-based electronics and optoelectronics are systematically reviewed. In addition, the functional devices and systems based on the piezotronics and piezo-phototronics in 2D-SMCs have been summarized. Finally, the research progresses are summarized, and future perspectives are proposed.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100131"},"PeriodicalIF":0.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Zero-power self-aware microsystem platform enabled by passive acoustic switch 无源声开关实现零功耗自感知微系统平台

Chip Pub Date : 2025-01-27 DOI: 10.1016/j.chip.2025.100130

Deng Yang , Xiaoqin Liu , Lingyun Zhang , Guozhe Xuan , Xiangzheng Sun , Jiahao Zhao

{"title":"Zero-power self-aware microsystem platform enabled by passive acoustic switch","authors":"Deng Yang , Xiaoqin Liu , Lingyun Zhang , Guozhe Xuan , Xiangzheng Sun , Jiahao Zhao","doi":"10.1016/j.chip.2025.100130","DOIUrl":"10.1016/j.chip.2025.100130","url":null,"abstract":"<div><div>Long-term continuous monitoring is essential for the Internet of Things (IoT), with efficient power use and sustainable energy supply as core challenges. This study presents a MEMS-based self-holding acoustic switch designed for uninterrupted monitoring of specific acoustic signals with zero power consumption. Microelectromechanical systems (MEMS) refer to miniaturized devices that integrate mechanical and electrical components on a single microchip. A mathematical model is developed to analyze the switch's acoustic frequency response. Simulations and experiments demonstrate its acoustic-driven properties. Acoustic switches with different structural parameters are designed, achieving resonant frequencies ranging from 192 Hz to 862 Hz. Electrostatic voltages are applied to enable self-holding functionality, and the acoustic switch exhibits a contact resistance as low as 29.3 Ω. The acoustic switch successfully performs various functions, including acoustic sensing, frequency identification, on–off control, and self-holding, all without drawing power from an external power supply. By integrating this acoustic switch, a zero-power self-aware microsystem platform is realized, allowing zero-power sleep states without closed-loop circuits while remaining responsive to target acoustic signals. This technology effectively supports long-term, large-scale deployment of unattended IoT terminals.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100130"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143937229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ferroelectric devices for artificial intelligence chips 用于人工智能芯片的铁电器件

Chip Pub Date : 2025-01-25 DOI: 10.1016/j.chip.2025.100129

Jinshun Bi , Muhammad Faizan , Xuefei Liu , Yue Ma , Xu Wang , Viktor Stempitsky

{"title":"Ferroelectric devices for artificial intelligence chips","authors":"Jinshun Bi , Muhammad Faizan , Xuefei Liu , Yue Ma , Xu Wang , Viktor Stempitsky","doi":"10.1016/j.chip.2025.100129","DOIUrl":"10.1016/j.chip.2025.100129","url":null,"abstract":"<div><div>The identification of ferroelectricity in oxides such as hafnium oxide, which are compatible with the contemporary semiconductor fabrication techniques, has contributed to a resurgence of ferroelectric devices in cutting-edge microelectronics. In a transistor structure, ferroelectric devices play the role of connecting a ferroelectric material to a semiconductor, which combines memory and logic operations at the level of a single device, thus meeting some of the most essential hardware requirements for new paradigms for artificial intelligence (A.I) chips. In this review, we addressed the issues associated with high-volume fabrication at advanced technology nodes (<span><math><mo>≤</mo><mn>10</mn><mspace></mspace><mi>nm</mi><mo>)</mo></math></span> at the material and device level. Moreover, we also reviewed the advancement of A.I chips such as neuro-inspired computer chips. For neuro-inspired A.I chips based on nonvolatile memory, four important metrics are suggested for benchmarking: computing density, energy efficiency, learning capability, and computing accuracy. It is inferred that ferroelectric devices can be a major hardware element in the design of future A.I chips, which will leads to an innovative approach to electronics that is termed ferroelectronics.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100129"},"PeriodicalIF":0.0,"publicationDate":"2025-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143898682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Generalized cross-entropy benchmarking for random circuits with ergodicity 遍历随机电路的广义交叉熵基准

Chip Pub Date : 2025-01-16 DOI: 10.1016/j.chip.2025.100127

Bin Cheng , Fei Meng , Zhi-Jiong Zhang , Man-Hong Yung

{"title":"Generalized cross-entropy benchmarking for random circuits with ergodicity","authors":"Bin Cheng , Fei Meng , Zhi-Jiong Zhang , Man-Hong Yung","doi":"10.1016/j.chip.2025.100127","DOIUrl":"10.1016/j.chip.2025.100127","url":null,"abstract":"<div><div>Cross-entropy benchmarking is a central technique adopted to certify a quantum chip in recent investigations. To better understand its mathematical foundation and develop new benchmarking schemes, the concept of ergodicity was introduced to random circuit sampling and it was found that the Haar random quantum circuit could satisfy an ergodicity condition—the average of certain types of postprocessing function over the output bit strings is close to the average over the unitary ensemble. For noiseless random circuits, it was proven that the ergodicity holds for polynomials of degree <em>t</em> with positive coefficients when the random circuits form a unitary 2<em>t</em>-design. For strong enough noise, the ergodicity condition is violated, which suggests that ergodicity is a property that can be exploited to certify a quantum chip. The deviation of ergodicity was formulated as a measure for quantum chip benchmarking, and it was demonstrated that it can be used to estimate the circuit fidelity for global depolarizing noise and weakly correlated noise. For a quadratic postprocessing function, our framework recovered Google's result on estimating the circuit fidelity via linear cross-entropy benchmarking (XEB), and we gave a sufficient condition on the noise model characterizing when such estimation is valid. The results establish an interesting connection between ergodicity and noise in random circuits and provide new insights into designing quantum benchmarking schemes.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100127"},"PeriodicalIF":0.0,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143881528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Self-powered asymmetric Schottky photodetector integrated with thin-film lithium niobate waveguide 集成薄膜铌酸锂波导的自供电非对称肖特基光电探测器

Chip Pub Date : 2025-01-14 DOI: 10.1016/j.chip.2025.100128

Youtian Hu , Qingyun Li , Fan Yang , Jing Hu , Ximing Li , Jiale Ou , Zhenjun Zang , Bangyi Zhu , Qinyu Zeng , Huangpu Han , Yujie Ma , Wang Zhang , Shuangchen Ruan , Bingxi Xiang

{"title":"Self-powered asymmetric Schottky photodetector integrated with thin-film lithium niobate waveguide","authors":"Youtian Hu , Qingyun Li , Fan Yang , Jing Hu , Ximing Li , Jiale Ou , Zhenjun Zang , Bangyi Zhu , Qinyu Zeng , Huangpu Han , Yujie Ma , Wang Zhang , Shuangchen Ruan , Bingxi Xiang","doi":"10.1016/j.chip.2025.100128","DOIUrl":"10.1016/j.chip.2025.100128","url":null,"abstract":"<div><div><strong>Thin-film lithium niobate (TFLN) is considered a crucial platform in</strong> <strong>next-generation</strong> <strong>integrated optoelectronics due to its excellent optical properties. Photodetectors are essential components for constructing fully functional photonic circuits. However, due to the low electrical conductivity and weak light absorption, TFLN cannot be directly used for fabricating photodetectors. In this study, we propose</strong><strong>d</strong> <strong>and demonstrate</strong><strong>d</strong> <strong>a</strong> <strong>high-performance</strong> <strong>MoTe</strong><sub><strong>2</strong></sub><strong>/TFLN heterostructure integrated Schottky photodetector operating at telecommunication wavelengths (1310 nm and 1550 nm). This structure enhances the photovoltaic effect by bending MoTe</strong><sub><strong>2</strong></sub> <strong>at the edge of one electrode, thereby achieving</strong> <strong>self-powered</strong> <strong>operation. At a wavelength of 1310 nm, the photodetector achieves a</strong> <strong>self-powered</strong> <strong>responsivity of 70 mA/W, which is among the highest for</strong> <strong>waveguide-integrated</strong> <strong>photodetectors. Additionally, due to the strong rectification effect of the Schottky junction, the photodetector exhibits an extremely low dark current of only 25 pA at −0.5 V bias voltage. The on/off ratios reach 2.6 × 10<sup>4</sup> at 0 V and 4.1 × 10<sup>4</sup> at −0.5 V bias. The</strong> <strong>self-powered</strong> <strong>response times</strong> <strong>were</strong> <strong>measured, showing fast response and recovery times of 160 μs and 169 μs, respectively.</strong></div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 2","pages":"Article 100128"},"PeriodicalIF":0.0,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143799507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0