A high-efficiency modeling method for analog integrated circuits

Abstract

Integrated circuits (ICs) are the foundation of information technology development. The optimal design scheme of an analog IC is determined by iteratively running the simulation software and comparing the performance metrics. However, the simulation software of an analog IC is time-consuming, which leads to the low design efficiency. Due to the nonideal factors in analog ICs, the nonlinear relationship between design parameters and performance metrics cannot be well described by the deduced approximation equations. Inspired by the image and semantic recognition, a universal high-efficiency modeling method for analog ICs based on convolutional neural network (CNN) was proposed in the current work, named as CNN-IC. The sparse topology mapping method was proposed to map the design parameters into a sparse matrix, which includes the spatial and transistor characteristics of analog IC. The CNN model with three convolutional kernels was constructed to extract “transistor-circuit module-integrate circuit” features level by level, which can replace the simulation software to effectively improve the training efficiency and accuracy. Two typical analog ICs were selected to verify the effectiveness of the CNN-IC model. The results show that the accuracy of the CNN-IC model could reach over 99% and that its convergence rate was the fastest compared with the machine learning models in the state of the art.