IF 7.1

Chip Pub Date : 2025-12-01 Epub Date: 2025-06-14 DOI: 10.1016/j.chip.2025.100157

Lijing Zhong , Yuying Wang , Xuhu Han , Jiacheng Hu , Jianrong Qiu

{"title":"Laser direct lithography of large-area three-dimensional integrated photonics: Technological challenges and advances","authors":"Lijing Zhong , Yuying Wang , Xuhu Han , Jiacheng Hu , Jianrong Qiu","doi":"10.1016/j.chip.2025.100157","DOIUrl":"10.1016/j.chip.2025.100157","url":null,"abstract":"<div><div>Integrated optics have been stuck in two-dimensional (2D) topologies for decades until the femtosecond laser direct writing (FLDW) technique enables direct lithography of three-dimensional (3D) geometries and nanoscale structures with rapid prototyping and large-scale manufacturing capabilities in a variety of transparent substrates. The 3D capability of FLDW makes diverse light-wave remapping geometries possible, thereby realizing efficient interconnection of optical systems at different spatial scales, offering a 3D integrated-optics footprint capable of scaling a benchtop optical system down to a 3D glass chip. This work summarizes the history and important milestones in developing FLDW waveguides. Basically, all revolutionary improvements in waveguide key performance, including low propagation loss and small bending radius, were accompanied by the discovery and development of new mechanisms for laser-induced refractive index modification. At the same time, advanced laser beam-shaping methods for tightly focused spatiotemporal fields have been technically grafted onto the fine control of laser–matter interaction in FLDW, notably achieving variable cross-section, arbitrary refractive index and mode-field distribution, thus providing new degrees of freedom beyond the limitations of traditional 2D planar waveguides for more complex photonics circuit design. In this work, we present a comprehensive review of the field, encompassing fundamental mechanisms (such as refractive index modification) as well as key technological advances that enable true 3D integration. On the basis of this, we summarize the basic integrated waveguide components fabricated by FLDW and point out the prospective challenges and future research directions. Tentative routes towards large-area, ultra-broadband, hybrid, multifunctional, all-optical system integration in 3D glass chips are also suggested.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100157"},"PeriodicalIF":7.1,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145527801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrated colloidal quantum dot devices for on-chip light sources 用于片上光源的集成胶体量子点器件

IF 7.1

Chip Pub Date : 2025-12-01 Epub Date: 2025-05-27 DOI: 10.1016/j.chip.2025.100152

Luwei Zhou , Yangzhi Tan , Dadi Tian , Taikang Ye , Fankai Zheng , Fengqi Qiu , Hechun Zhang , Nan Zhang , Mingjie Li , Xiao Wei Sun , Hoi Wai Choi , Dan Wu , Kai Wang

{"title":"Integrated colloidal quantum dot devices for on-chip light sources","authors":"Luwei Zhou , Yangzhi Tan , Dadi Tian , Taikang Ye , Fankai Zheng , Fengqi Qiu , Hechun Zhang , Nan Zhang , Mingjie Li , Xiao Wei Sun , Hoi Wai Choi , Dan Wu , Kai Wang","doi":"10.1016/j.chip.2025.100152","DOIUrl":"10.1016/j.chip.2025.100152","url":null,"abstract":"<div><div>The rapid advancement of photonic integrated circuits (PICs) has presented a promising solution to meet future demands for faster data transmission, broader bandwidth, and lower power consumption. However, the indirect bandgap of silicon presents challenges in achieving optical gain, necessitating the integration of III-V materials through complex and costly bonding or epitaxial techniques. In this context, colloidal quantum dots (CQDs) have emerged as a viable alternative for on-chip light sources due to their unique properties, including cost-effective synthesis, high photoluminescence quantum yield, precisely tunable emission wavelengths across visible to near-infrared, and excellent solution processability. These distinct advantages position CQDs as promising components for next-generation optoelectronic devices, fueling advancements in fields such as telecommunications, sensing, and display technologies. In this review, we systematically examine the structural evolution of CQDs aiming at luminescent property enhancement and explore their integration with various photonic platforms. Key applications are discussed, focusing on waveguide-coupled CQD light-emitting diodes and lasers, metasurface-integrated CQD lasers, and cavity-coupled CQD single-photon sources. Additionally, this review presents recent efforts in promoting electrically pumped CQD lasers, highlighting the potential of CQD light sources to revolutionize on-chip photonic systems. Finally, we present prospects for further development of CQD-based on-chip light sources, emphasizing their role in the future of integrated photonics.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100152"},"PeriodicalIF":7.1,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145424569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A C-band cryogenic gallium arsenide low-noise amplifier for quantum applications 用于量子应用的c波段低温砷化镓低噪声放大器

IF 7.1

Chip Pub Date : 2025-12-01 Epub Date: 2025-04-03 DOI: 10.1016/j.chip.2025.100146

Zechen Guo , Daxiong Sun , Peisheng Huang , Xuandong Sun , Yuefeng Yuan , Jiawei Zhang , Wenhui Huang , Yongqi Liang , Jiawei Qiu , Jiajian Zhang , Ji Chu , Weijie Guo , Ji Jiang , Jingjing Niu , Wenhui Ren , Ziyu Tao , Xiayu Linpeng , Youpeng Zhong , Dapeng Yu

{"title":"A C-band cryogenic gallium arsenide low-noise amplifier for quantum applications","authors":"Zechen Guo , Daxiong Sun , Peisheng Huang , Xuandong Sun , Yuefeng Yuan , Jiawei Zhang , Wenhui Huang , Yongqi Liang , Jiawei Qiu , Jiajian Zhang , Ji Chu , Weijie Guo , Ji Jiang , Jingjing Niu , Wenhui Ren , Ziyu Tao , Xiayu Linpeng , Youpeng Zhong , Dapeng Yu","doi":"10.1016/j.chip.2025.100146","DOIUrl":"10.1016/j.chip.2025.100146","url":null,"abstract":"<div><div>Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNAs) for qubit readout. Here we presented a C-band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on a 150 nm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance matching to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third stages enhances the overall stability. Moreover, the pHEMT self-bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only a single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a minimum noise temperature of 4 K and an average gain of 40 dB. We further benchmarked this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100146"},"PeriodicalIF":7.1,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Controllable floating gate memory performance through device structure design 通过器件结构设计实现可控浮栅存储器性能

IF 7.1

Chip Pub Date : 2025-12-01 Epub Date: 2025-05-20 DOI: 10.1016/j.chip.2025.100151

Ruitong Bie , Ce Li , Zirui Zhang , Tianze Yu , Dongliang Yang , Binghe Liu , Linfeng Sun

{"title":"Controllable floating gate memory performance through device structure design","authors":"Ruitong Bie , Ce Li , Zirui Zhang , Tianze Yu , Dongliang Yang , Binghe Liu , Linfeng Sun","doi":"10.1016/j.chip.2025.100151","DOIUrl":"10.1016/j.chip.2025.100151","url":null,"abstract":"<div><div>Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attributed to variations in material thickness or interface quality without a detailed exploration. Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory. Here, we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions. For the first time, the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated. Moreover, controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated. The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100151"},"PeriodicalIF":7.1,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144890739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb) 基于单层GeX2 （X = As, Sb）的N型和p型亚10nm高性能晶体管

Chip Pub Date : 2025-12-01 Epub Date: 2025-03-29 DOI: 10.1016/j.chip.2025.100144

Siyu Yang, Hao Shi, Yang Hu, Xinwei Guo, Xiaojia Yuan, Hengze Qu, Haibo Zeng, Shengli Zhang

{"title":"N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb)","authors":"Siyu Yang, Hao Shi, Yang Hu, Xinwei Guo, Xiaojia Yuan, Hengze Qu, Haibo Zeng, Shengli Zhang","doi":"10.1016/j.chip.2025.100144","DOIUrl":"10.1016/j.chip.2025.100144","url":null,"abstract":"<div><div>Exploring silicon alternatives for channel material is crucial for next-generation integrated circuits, two-dimensional (2D) materials are the most promising candidates due to their capability to suppress short-channel effects. In this study, we conducted simulations on the structural and electronic properties of 2D GeX<sub>2</sub> (X = As, Sb), as well as the ballistic transport characteristics of sub-10 nm n- and p-type 2D GeX<sub>2</sub> field effect transistors (FETs) based on first principles. The key metrics in terms of on-state current (<em>I</em><sub>on</sub>), delay time, and power consumption of n-type GeAs<sub>2</sub> and p-type GeSb<sub>2</sub> FETs can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices until the gate length (<em>L</em><sub>g</sub>) is shrunk to 5 nm. Specifically, the <em>I</em><sub>on</sub> of n-type GeAs<sub>2</sub> FET and p-type GeSb<sub>2</sub> FET reaches 2299 and 1480 μA/μm when <em>L</em><sub>g</sub> is 7 nm, surpassing InSe, MoS<sub>2</sub><sub>,</sub> and WSe<sub>2</sub> FETs. Our work highlights the potential of 2D GeX<sub>2</sub> in future nanoelectronics.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 4","pages":"Article 100144"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144679711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

GaN chips for monitoring density and temperature of lead-acid batteries 用于监测铅酸电池密度和温度的氮化镓芯片

Chip Pub Date : 2025-09-01 Epub Date: 2025-02-25 DOI: 10.1016/j.chip.2025.100133

Zhiyong Ye , Ganyuan Deng , Dongmiao Liu , Jingyan Wang , Xiaodi Gao , Kwai Hei Li , Ling Zhu

{"title":"GaN chips for monitoring density and temperature of lead-acid batteries","authors":"Zhiyong Ye , Ganyuan Deng , Dongmiao Liu , Jingyan Wang , Xiaodi Gao , Kwai Hei Li , Ling Zhu","doi":"10.1016/j.chip.2025.100133","DOIUrl":"10.1016/j.chip.2025.100133","url":null,"abstract":"<div><div>Lead-acid batteries are indispensable in various applications, and it is crucial to monitor their status. However, the existing sensing units for lead-acid batteries are limited by their bulky size, slow response time, and lack of temperature sensing and compensation capabilities. In the current work, a compact GaN-based sensing device was proposed to simultaneously measure the electrolyte density and temperature. The device comprises a light-emitting diode (LED) and a photodetector (PD) integrated on a GaN-on-sapphire chip in a monolithic configuration. The forward voltage of the LED reflects the electrolyte temperature, while the photocurrent of the PD varies with electrolyte density due to optical reflection changes at the exposed sapphire interface. The measured signals were processed using a decoupling matrix to achieve temperature compensation. The device exhibits a sensitivity of −29.1 μA/(g/cm<sup>3</sup>) for density in the range of 1.09 g/cm<sup>3</sup> to 1.29 g/cm<sup>3</sup>, and -1.07 mV/°C for temperature in the range of 25 to 45 °C. The performance of the device was also validated through comparisons with commercial meters and real-time monitoring during the charging and discharging of the batteries. The device has notable advantages in size, cost, and fast response/recovery time (134.3/201.4 ms), rendering it a promising tool for monitoring lead-acid batteries.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100133"},"PeriodicalIF":0.0,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144261297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-efficiency modeling method for analog integrated circuits 模拟集成电路的一种高效建模方法

Chip Pub Date : 2025-09-01 Epub Date: 2025-03-07 DOI: 10.1016/j.chip.2025.100135

Dongdong Chen , Yunqi Yang , Xianglong Wang , Di Li , Guoqing Xin , Yintang Yang

{"title":"A high-efficiency modeling method for analog integrated circuits","authors":"Dongdong Chen , Yunqi Yang , Xianglong Wang , Di Li , Guoqing Xin , Yintang Yang","doi":"10.1016/j.chip.2025.100135","DOIUrl":"10.1016/j.chip.2025.100135","url":null,"abstract":"<div><div>Integrated circuits (ICs) are the foundation of information technology development. The optimal design scheme of an analog IC is determined by iteratively running the simulation software and comparing the performance metrics. However, the simulation software of an analog IC is time-consuming, which leads to the low design efficiency. Due to the nonideal factors in analog ICs, the nonlinear relationship between design parameters and performance metrics cannot be well described by the deduced approximation equations. Inspired by the image and semantic recognition, a universal high-efficiency modeling method for analog ICs based on convolutional neural network (CNN) was proposed in the current work, named as CNN-IC. The sparse topology mapping method was proposed to map the design parameters into a sparse matrix, which includes the spatial and transistor characteristics of analog IC. The CNN model with three convolutional kernels was constructed to extract “transistor-circuit module-integrate circuit” features level by level, which can replace the simulation software to effectively improve the training efficiency and accuracy. Two typical analog ICs were selected to verify the effectiveness of the CNN-IC model. The results show that the accuracy of the CNN-IC model could reach over 99% and that its convergence rate was the fastest compared with the machine learning models in the state of the art.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100135"},"PeriodicalIF":0.0,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144338906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Root cause of read after delay in ferroelectric memories 铁电存储器延迟后读取的根本原因

Chip Pub Date : 2025-09-01 Epub Date: 2025-03-16 DOI: 10.1016/j.chip.2025.100139

Diqing Su , Shaorui Li , Xiao Wang , Yannan Xu , Qingting Ding , Heng Zhang , Hangbing Lyu

{"title":"Root cause of read after delay in ferroelectric memories","authors":"Diqing Su , Shaorui Li , Xiao Wang , Yannan Xu , Qingting Ding , Heng Zhang , Hangbing Lyu","doi":"10.1016/j.chip.2025.100139","DOIUrl":"10.1016/j.chip.2025.100139","url":null,"abstract":"<div><div>Accelerated margin loss during read after delay (RAD) is a newly discovered reliability concern in HfO<sub>2</sub>-based ferroelectric random access memories (FeRAMs), which significantly impacts the lifetime of the memory device. Unlike conventional fatigue effect, this issue is closely linked to the coercive field (<span><math><mrow><msub><mi>E</mi><mi>c</mi></msub></mrow></math></span>) shift, or imprint, during bipolar electrical field cycling at intermediate frequency. The precise cause of imprint during RAD, however, remains elusive. To investigate, we employed customized electrical testing to examine the charge transfer behavior in static imprint (SI) and continuous read/write (CRW) scenarios, which can be viewed as RAD performed at minimum and maximum frequencies. Our findings reveal that interfacial charge injection is the primary mechanism for imprint in SI, while bulk charge drives the imprint in asymmetric CRW. Further exploration with a SPICE-based charge transfer model suggests that RAD-related imprint is the result of bulk charge migration, driven by the periodically restored depolarization field after read/write-back operation. Experimental verification supports this theory, highlighting the importance of interface engineering to enhance bound charge screening and element doping to elevate the migration barrier for bulk charges in addressing the RAD problem.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100139"},"PeriodicalIF":0.0,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144306710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On-chip differential mode group delay manipulation based on 3D waveguides 基于三维波导的片上差分模群延迟处理

Chip Pub Date : 2025-09-01 Epub Date: 2025-03-08 DOI: 10.1016/j.chip.2025.100137

Xiaofeng Liu , Quandong Huang , Jiaqi Ran , Jiali Zhang , Ou Xu , Di Peng , Yuwen Qin

{"title":"On-chip differential mode group delay manipulation based on 3D waveguides","authors":"Xiaofeng Liu , Quandong Huang , Jiaqi Ran , Jiali Zhang , Ou Xu , Di Peng , Yuwen Qin","doi":"10.1016/j.chip.2025.100137","DOIUrl":"10.1016/j.chip.2025.100137","url":null,"abstract":"<div><div>Mode-division multiplexing based on few-mode optical fiber is a promising technology to increase the transmission capacity of optical communication systems, where multi-input multi-output (MIMO) digital signal processing (DSP) is employed to (de)multiplex the signals from different mode channels. Since the group velocity of each mode is different, the signals are separated in the time domain when they reach the receivers. Therefore, it is necessary to compensate for the mode-group-velocity delay of the interval modes to reduce the complexity of the MIMO-DSP algorithm. In this work, we demonstrated an on-chip differential-mode group delay (DMGD) manipulating device based on 3D multilayer cladding waveguides. The proposed device supports compensating the DMGD of about 10.0 ps/m with a device formed with a low refractive index difference. In the meanwhile, the value of DMGD can be greatly improved to be 1878.6 ps/m by forming the device with high refractive index difference material such as thin-film lithium niobate with silicon dioxide cladding. The proposed device provides a feasible design for on-chip DMGD manipulation, which can find various applications in the mode division multiplexing system.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100137"},"PeriodicalIF":0.0,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

All-optical Fourier neural network using partially coherent light 采用部分相干光的全光傅立叶神经网络

Chip Pub Date : 2025-09-01 Epub Date: 2025-03-16 DOI: 10.1016/j.chip.2025.100140

Jianwei Qin , Yanbing Liu , Yan Liu , Xun Liu , Wei Li , Fangwei Ye

{"title":"All-optical Fourier neural network using partially coherent light","authors":"Jianwei Qin , Yanbing Liu , Yan Liu , Xun Liu , Wei Li , Fangwei Ye","doi":"10.1016/j.chip.2025.100140","DOIUrl":"10.1016/j.chip.2025.100140","url":null,"abstract":"<div><div>Optical neural networks present distinct advantages over traditional electrical counterparts, such as accelerated data processing and reduced energy consumption. While coherent light is conventionally used in optical neural networks, our study proposed harnessing spatially incoherent light in all-optical Fourier neural networks. Contrary to natural predictions of declining target recognition accuracy with increased incoherence, our experimental results demonstrated a surprising outcome: improved accuracy with incoherent light. We attribute this enhancement to spatially incoherent light's ability to alleviate experimental errors like diffraction rings and laser speckle. Our experiments introduced controllable spatial incoherence by passing monochromatic light through a spatial light modulator featuring a dynamically changing random phase array. These findings underscore partially coherent light's potential to optimize optical neural networks, delivering dependable and efficient solutions for applications demanding consistent accuracy and robustness across diverse conditions, including on-chip optical computing, photonic interconnects, and reconfigurable optical processors.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"4 3","pages":"Article 100140"},"PeriodicalIF":0.0,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144569814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

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