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Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy 通过非对称电极接触策略实现通道偏压控制的可重构硅纳米线晶体管
Chip Pub Date : 2024-09-01 DOI: 10.1016/j.chip.2024.100098
{"title":"Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy","authors":"","doi":"10.1016/j.chip.2024.100098","DOIUrl":"10.1016/j.chip.2024.100098","url":null,"abstract":"<div><p>Reconfigurable field-effect transistors (R-FETs) that can dynamically reconfigure the transistor polarity, from n-type to p-type channel or vice versa, represent a promising new approach to reduce the logic complexity and granularity of programmable electronics. Although R-FETs have been successfully demonstrated upon silicon nanowire (SiNW) channels, a pair of extra program gates is still needed to control the source/drain (S/D) contacts. In this work, we propose a rather simple single gate R-FET structure with an asymmetric S/D electrode contact, where the FET channel polarity can be altered by changing the sign of channel bias <em>V</em><sub>ds</sub>. These R-FETs were fabricated upon an orderly array of planar SiNW channels, grown via in-plane solid-liquid-solid mechanism, and contacted by Ti/Al and Pt/Au at the S/D electrodes, respectively. Remarkably, this channel-bias-controlled R-FET strategy has been successfully testified and implemented upon both p-type-doped (with indium dopants) or n-type-doped (phosphorus) SiNW channels, whereas the R-FET prototypes demonstrate an impressive high <em>I</em><sub>on/off</sub> ratio of &gt; 10<sup>6</sup> and a steep subthreshold swing of 79 mV/dec. These results indicate a rather simple, compact and generic enough R-FET strategy for the construction of a new generation of SiNW-based programmable and low-power electronics.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 3","pages":"Article 100098"},"PeriodicalIF":0.0,"publicationDate":"2024-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000169/pdfft?md5=e3070abd5dfb82b3bdcb7e25f29beb8d&pid=1-s2.0-S2709472324000169-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141411691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Highly sensitive diamond X-ray detector array for high-temperature applications 用于高温应用的高灵敏度金刚石 X 射线探测器阵列
Chip Pub Date : 2024-09-01 DOI: 10.1016/j.chip.2024.100106
Wenjie Dou , Chaonan Lin , Wei Fan , Xun Yang , Chao Fang , Huaping Zang , Shaoyi Wang , Congxu Zhu , Zhi Zheng , Weimin Zhou , Chongxin Shan
{"title":"Highly sensitive diamond X-ray detector array for high-temperature applications","authors":"Wenjie Dou ,&nbsp;Chaonan Lin ,&nbsp;Wei Fan ,&nbsp;Xun Yang ,&nbsp;Chao Fang ,&nbsp;Huaping Zang ,&nbsp;Shaoyi Wang ,&nbsp;Congxu Zhu ,&nbsp;Zhi Zheng ,&nbsp;Weimin Zhou ,&nbsp;Chongxin Shan","doi":"10.1016/j.chip.2024.100106","DOIUrl":"10.1016/j.chip.2024.100106","url":null,"abstract":"<div><div>Diamond is a highly suitable material for X-ray detectors that can function effectively in harsh environments due to its unique properties such as ultrawide bandgap, high radiation resistance, excellent carrier mobility as well as remarkable chemical and thermal stability. However, the sensitivity of diamond X-ray detectors needs further improvement due to the relatively low X-ray absorption efficiency of diamond, and the exploration of single-crystal diamond array imaging still remains unexplored. In the current work, a 10 × 10 X-ray photodetector array was constructed from single-crystal diamond. To improve the sensitivity of the diamond X-ray detector, an asymmetric sandwich electrode structure was utilized. Additionally, trenches were created through laser cutting to prevent crosstalk between adjacent pixels. The diamond X-ray detector array exhibits exceptional performance, including a low detection limit of 4.9 nGy s<sup>−1</sup>, a sensitivity of 14.3 mC Gy<sup>−1</sup> cm<sup>−2</sup>, and a light-dark current ratio of 18,312, which are among the most favorable values ever reported for diamond X-ray detectors. Furthermore, these diamond X-ray detectors can operate at high temperatures up to 450 °C, making them suitable for development in harsh environments.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 3","pages":"Article 100106"},"PeriodicalIF":0.0,"publicationDate":"2024-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000248/pdfft?md5=641348a92d64c73eaa83ace8518de946&pid=1-s2.0-S2709472324000248-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142206231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges and recent advances in HfO2-based ferroelectric films for non-volatile memory applications 非易失性存储器应用中基于 HfO2 的铁电薄膜所面临的挑战和最新进展
Chip Pub Date : 2024-09-01 DOI: 10.1016/j.chip.2024.100101
{"title":"Challenges and recent advances in HfO2-based ferroelectric films for non-volatile memory applications","authors":"","doi":"10.1016/j.chip.2024.100101","DOIUrl":"10.1016/j.chip.2024.100101","url":null,"abstract":"<div><div>The emergence of data-centric applications such as artificial intelligence (AI), machine learning, and the Internet of Things (IoT), has promoted surges in demand for storage memories with high operating speed and nonvolatile characteristics. HfO<sub>2</sub>-based ferroelectric memory technologies, which emerge as a promising alternative, have attracted considerable attention due to their high performance, energy efficiency, and full compatibility with the standard complementary metal-oxide-semiconductors (CMOS) process. These nonvolatile storage elements, such as ferroelectric random access memory (FeRAM), ferroelectric field-effect transistors (FeFETs), and ferroelectric tunnel junctions (FTJs), possess different data access mechanisms, individual merits, and specific application boundaries in next-generation memories or even beyond von Neumann architecture. This paper provides an overview of ferroelectric HfO<sub>2</sub> memory technologies, addresses the current challenges, and offers insights into future research directions and prospects.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 3","pages":"Article 100101"},"PeriodicalIF":0.0,"publicationDate":"2024-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141394538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A universal optoelectronic imaging platform with wafer-scale integration of two-dimensional semiconductors 二维半导体晶圆级集成的通用光电成像平台
Chip Pub Date : 2024-08-08 DOI: 10.1016/j.chip.2024.100107
Xinyu Wang , Die Wang , Yuchen Tian , Jing Guo , Jinshui Miao , Weida Hu , Hailu Wang , Kang Liu , Lei Shao , Saifei Gou , Xiangqi Dong , Hesheng Su , Chuming Sheng , Yuxuan Zhu , Zhejia Zhang , Jinshu Zhang , Qicheng Sun , Zihan Xu , Peng Zhou , Honglei Chen , Wenzhong Bao
{"title":"A universal optoelectronic imaging platform with wafer-scale integration of two-dimensional semiconductors","authors":"Xinyu Wang ,&nbsp;Die Wang ,&nbsp;Yuchen Tian ,&nbsp;Jing Guo ,&nbsp;Jinshui Miao ,&nbsp;Weida Hu ,&nbsp;Hailu Wang ,&nbsp;Kang Liu ,&nbsp;Lei Shao ,&nbsp;Saifei Gou ,&nbsp;Xiangqi Dong ,&nbsp;Hesheng Su ,&nbsp;Chuming Sheng ,&nbsp;Yuxuan Zhu ,&nbsp;Zhejia Zhang ,&nbsp;Jinshu Zhang ,&nbsp;Qicheng Sun ,&nbsp;Zihan Xu ,&nbsp;Peng Zhou ,&nbsp;Honglei Chen ,&nbsp;Wenzhong Bao","doi":"10.1016/j.chip.2024.100107","DOIUrl":"10.1016/j.chip.2024.100107","url":null,"abstract":"<div><div>Photodetectors (PDs) are crucial in modern society as they enable the detection of a diverse range of light-based signals. With the exponential increase in their development, materials are being used to create a wide range of PDs that play critical roles in enabling various applications and technologies. Image sensor technology has been hindered due to the lack of a universal system that can integrate all types of PDs with silicon-based readout integrated circuits (ROICs). To address this issue, we conducted experiments adopting two-dimensional materials as an example. High-performance MoS<sub>2</sub>-/MoTe<sub>2</sub>-based PDs were fabricated in the current work and the most suitable ROICs were identified to pair with them. This established a solid foundation for further researches in the field of image sensors. We developed and implemented a versatile testing system that uses a printed circuit board to connect the PD and ROIC. After the ROIC generates the sampled signal, it is collected and processed by algorithms, which overcome device uniformity limitations and produce a high-quality image that is visible to the naked eye. This universal system can be used with a wide range of PD and ROIC types made from different materials, making it highly convenient for diverse testing applications and the development of diverse image sensor types. This robust new platform is expected to spur further innovation and advancements in this rapidly developing field.</div></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 4","pages":"Article 100107"},"PeriodicalIF":0.0,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142206230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Corrigendum to “Wang, Z. et al. Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing” Chip 2 (2023) 100044 范德华铁电晶体管:用于高精度神经形态计算的全方位人工突触 "的更正,Chip 2 (2023) 100044
Chip Pub Date : 2024-07-01 DOI: 10.1016/j.chip.2024.100100
Zhongwang Wang, Xuefan Zhou, Xiaochi Liu, Aocheng Qiu, Caifang Gao, Yahua Yuan, Yumei Jing, Dou Zhang, Wenwu Li, Hang Luo, Junhao Chu, Jian Sun
{"title":"Corrigendum to “Wang, Z. et al. Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing” Chip 2 (2023) 100044","authors":"Zhongwang Wang, Xuefan Zhou, Xiaochi Liu, Aocheng Qiu, Caifang Gao, Yahua Yuan, Yumei Jing, Dou Zhang, Wenwu Li, Hang Luo, Junhao Chu, Jian Sun","doi":"10.1016/j.chip.2024.100100","DOIUrl":"https://doi.org/10.1016/j.chip.2024.100100","url":null,"abstract":"","PeriodicalId":100244,"journal":{"name":"Chip","volume":"9 6","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141700701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Remote electric powering by germanium photovoltaic conversion of an Erbium-fiber laser beam 通过锗光电转换铒光纤激光束实现远程供电
Chip Pub Date : 2024-06-26 DOI: 10.1016/j.chip.2024.100099
Richard Soref , Francesco De Leonardis , Oussama Moutanabbir , Gerard Daligou
{"title":"Remote electric powering by germanium photovoltaic conversion of an Erbium-fiber laser beam","authors":"Richard Soref ,&nbsp;Francesco De Leonardis ,&nbsp;Oussama Moutanabbir ,&nbsp;Gerard Daligou","doi":"10.1016/j.chip.2024.100099","DOIUrl":"10.1016/j.chip.2024.100099","url":null,"abstract":"<div><p>The commercially available 4000-Watt continuous-wave (CW) Erbium-doped-fiber laser, emitting at the 1567-nm wavelength where the atmosphere has high transmission, provides an opportunity for harvesting electric power at remote “off the grid” locations using a multi-module photovoltaic (PV) “receiver” panel. This paper proposes a 32-element monocrystalline thick-layer Germanium PV panel for efficient harvesting of a collimated 1.13-m-diam beam. The 0.78-m<sup>2</sup> PV panel is constructed from commercial Ge wafers. For incident CW laser-beam power in the 4000 to 10,000 W range, our thermal, electrical, and infrared simulations predict 660 to 1510 Watts of electrical output at the panel temperatures of 350 to 423 K.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 3","pages":"Article 100099"},"PeriodicalIF":0.0,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000170/pdfft?md5=d0ba424633e8badf6dfa158686b16e97&pid=1-s2.0-S2709472324000170-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141722083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The on-chip thermoelectric cooler: advances, applications and challenges 片上热电冷却器:进展、应用和挑战
Chip Pub Date : 2024-06-01 DOI: 10.1016/j.chip.2024.100096
Chengjun Li, Yubo Luo, Wang Li, Boyu Yang, Chengwei Sun, Wenyuan Ma, Zheng Ma, Yingchao Wei, Xin Li, Junyou Yang
{"title":"The on-chip thermoelectric cooler: advances, applications and challenges","authors":"Chengjun Li,&nbsp;Yubo Luo,&nbsp;Wang Li,&nbsp;Boyu Yang,&nbsp;Chengwei Sun,&nbsp;Wenyuan Ma,&nbsp;Zheng Ma,&nbsp;Yingchao Wei,&nbsp;Xin Li,&nbsp;Junyou Yang","doi":"10.1016/j.chip.2024.100096","DOIUrl":"10.1016/j.chip.2024.100096","url":null,"abstract":"<div><p>With the development of 5G technology and increasing chip integration, traditional active cooling methods struggle to meet the growing thermal demands of chips. Thermoelectric coolers (TECs) have garnered great attention due to their rapid response, significant cooling differentials, strong compatibility, high stability and controllable device dimensions. In this review, starting from the fundamental principles of thermoelectric cooling and device design, high-performance thermoelectric cooling materials are summarized, and the progress of advanced on-chip TECs is comprehensively reviewed. Finally, the paper outlines the challenges and opportunities in TEC design, performance and applications, laying great emphasis on the critical role of thermoelectric cooling in addressing the evolving thermal management requirements in the era of emerging chip technologies.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100096"},"PeriodicalIF":0.0,"publicationDate":"2024-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000145/pdfft?md5=5df7bff3a72f84dd9ee90367220d271d&pid=1-s2.0-S2709472324000145-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140792827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Large-area growth of synaptic heterostructure arrays for integrated neuromorphic visual perception chips 用于集成神经形态视觉感知芯片的大面积生长突触异质结构阵列
Chip Pub Date : 2024-06-01 DOI: 10.1016/j.chip.2024.100088
Yao Deng , Shenghong Liu , Manshi Li , Na Zhang , Yiming Feng , Junbo Han , Yury Kapitonov , Yuan Li , Tianyou Zhai
{"title":"Large-area growth of synaptic heterostructure arrays for integrated neuromorphic visual perception chips","authors":"Yao Deng ,&nbsp;Shenghong Liu ,&nbsp;Manshi Li ,&nbsp;Na Zhang ,&nbsp;Yiming Feng ,&nbsp;Junbo Han ,&nbsp;Yury Kapitonov ,&nbsp;Yuan Li ,&nbsp;Tianyou Zhai","doi":"10.1016/j.chip.2024.100088","DOIUrl":"10.1016/j.chip.2024.100088","url":null,"abstract":"<div><p>Two-dimensional metal chalcogenides have garnered significant attention as promising candidates for novel neuromorphic synaptic devices due to their exceptional structural and optoelectronic properties. However, achieving large-scale integration and practical applications of synaptic chips has proven to be challenging due to significant hurdles in materials preparation and the absence of effective nanofabrication techniques. In a recent breakthrough, we introduced a revolutionary allopatric defect-modulated Fe<sub>7</sub>S<sub>8</sub>@MoS<sub>2</sub> synaptic heterostructure, which demonstrated remarkable optoelectronic synaptic response capabilities. Building upon this achievement, our current study takes a step further by presenting a sulfurization-seeding synergetic growth strategy, enabling the large-scale and arrayed preparation of Fe<sub>7</sub>S<sub>8</sub>@MoS<sub>2</sub> heterostructures. Moreover, a three-dimensional vertical integration technique was developed for the fabrication of arrayed optoelectronic synaptic chips. Notably, we have successfully simulated the visual persistence function of the human eye with the adoption of the arrayed chip. Our synaptic devices exhibit a remarkable ability to replicate the preprocessing functions of the human visual system, resulting in significantly improved noise reduction and image recognition efficiency. This study might mark an important milestone in advancing the field of optoelectronic synaptic devices, which significantly prompts the development of mature integrated visual perception chips.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100088"},"PeriodicalIF":0.0,"publicationDate":"2024-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000066/pdfft?md5=3c43e3097235258d0932a5944fcc9d1f&pid=1-s2.0-S2709472324000066-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140406791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon cross-coupled gated tunneling diodes 硅交叉耦合门控隧道二极管
Chip Pub Date : 2024-06-01 DOI: 10.1016/j.chip.2024.100094
Zhenyun Tang , Zhe Wang , Zhigang Song , Wanhua Zheng
{"title":"Silicon cross-coupled gated tunneling diodes","authors":"Zhenyun Tang ,&nbsp;Zhe Wang ,&nbsp;Zhigang Song ,&nbsp;Wanhua Zheng","doi":"10.1016/j.chip.2024.100094","DOIUrl":"10.1016/j.chip.2024.100094","url":null,"abstract":"<div><p><strong>Tunneling-based static</strong> <strong>random-access</strong> <strong>memory (SRAM) devices ha</strong><strong>ve</strong> <strong>been developed to fulfill the demands of high density and low power,</strong> <strong>and</strong> <strong>the performance of SRAMs</strong> <strong>has also been greatly promoted</strong><strong>.</strong> <strong>However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be filled</strong><strong>.</strong> <strong>Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon cross-coupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology</strong><strong>. With</strong> <strong>t</strong>echnology computer aided design (<strong>TCAD</strong><strong>)</strong> <strong>simulations, it has been validated that this type of device</strong> <strong>not only exhibit</strong><strong>s</strong> <strong>significant</strong> <strong>negative-differential-resistance</strong> <strong>(NDR) behavior with PVCRs up to 10</strong><sup><strong>6</strong></sup><strong>, but also possess</strong><strong>es</strong> <strong>reasonable process margins. Moreover, SPICE simulation</strong> <strong>showed</strong> <strong>the great potential of such devices to achieve</strong> <strong>ultralow-power</strong> <strong>tunneling-based SRAMs with standby power down to 10</strong><sup><strong>−12</strong></sup> <strong>W.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100094"},"PeriodicalIF":0.0,"publicationDate":"2024-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000121/pdfft?md5=ea45c5d42cfca2586f9abf13cbf43f07&pid=1-s2.0-S2709472324000121-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140782378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memristor-based spiking neural networks: cooperative development of neural network architecture/algorithms and memristors 基于 Memristor 的尖峰神经网络:神经网络架构/算法与 Memristor 的合作开发
Chip Pub Date : 2024-06-01 DOI: 10.1016/j.chip.2024.100093
Huihui Peng, Lin Gan, Xin Guo
{"title":"Memristor-based spiking neural networks: cooperative development of neural network architecture/algorithms and memristors","authors":"Huihui Peng,&nbsp;Lin Gan,&nbsp;Xin Guo","doi":"10.1016/j.chip.2024.100093","DOIUrl":"10.1016/j.chip.2024.100093","url":null,"abstract":"<div><p>Inspired by the structure and principles of the human brain, spike neural networks (SNNs) appear as the latest generation of artificial neural networks, attracting significant and universal attention due to their remarkable low-energy transmission by pulse and powerful capability for large-scale parallel computation. Current research on artificial neural networks gradually change from software simulation into hardware implementation. However, such a process is fraught with challenges. In particular, memristors are highly anticipated hardware candidates owing to their fast-programming speed, low power consumption, and compatibility with the complementary metal–oxide semiconductor (CMOS) technology. In this review, we start from the basic principles of SNNs, and then introduced memristor-based technologies for hardware implementation of SNNs, and further discuss the feasibility of integrating customized algorithm optimization to promote efficient and energy-saving SNN hardware systems. Finally, based on the existing memristor technology, we summarize the current problems and challenges in this field.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100093"},"PeriodicalIF":0.0,"publicationDate":"2024-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S270947232400011X/pdfft?md5=45bccc10058e80fbaed47545c5fd2f62&pid=1-s2.0-S270947232400011X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140767491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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