IEEE open journal of circuits and systems最新文献_第6页

Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers 分析宽带接收器中作为连续时间放大器替代品的离散时间积分放大器

IEEE open journal of circuits and systems Pub Date : 2023-12-01 DOI: 10.1109/OJCAS.2023.3338210

Yudhajit Ray;Shreyas Sen

{"title":"Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers","authors":"Yudhajit Ray;Shreyas Sen","doi":"10.1109/OJCAS.2023.3338210","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3338210","url":null,"abstract":"Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"347-362"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10337627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery 波特率多级时钟和数据恢复混合定时误差检测器

IEEE open journal of circuits and systems Pub Date : 2023-11-27 DOI: 10.1109/OJCAS.2023.3335400

Ahmed Abdelaziz;Mohamed Ahmed;Tawfiq Musah

引用次数: 0

A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm 基于阶梯逆变器DTC的65nm高能效边缘计算116 TOPS/W空间展开时域加速器

IEEE open journal of circuits and systems Pub Date : 2023-11-15 DOI: 10.1109/OJCAS.2023.3332853

Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari

{"title":"A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm","authors":"Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari","doi":"10.1109/OJCAS.2023.3332853","DOIUrl":"10.1109/OJCAS.2023.3332853","url":null,"abstract":"The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 compared to prior time-domain accelerators.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"308-323"},"PeriodicalIF":0.0,"publicationDate":"2023-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10318175","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135710807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Class–CTA: Concept and Theoretical Analysis of a High Linearity and Efficiency Power Stage Architecture cta:高线性和高效率功率级架构的概念和理论分析

IEEE open journal of circuits and systems Pub Date : 2023-11-02 DOI: 10.1109/OJCAS.2023.3329723

Dimitrios Baxevanakis;Dimitris Nikitas;Paul P. Sotiriadis

引用次数: 0

A Study of Out-of-Band Emission in Digital Transmitters Due to PLL Phase Noise, Circuit Non-Linearity, and Bandwidth Limitation 锁相环相位噪声、电路非线性和带宽限制对数字发射机带外发射的影响研究

IEEE open journal of circuits and systems Pub Date : 2023-11-02 DOI: 10.1109/OJCAS.2023.3328871

Mohammad Oveisi;Seyedali Hosseinisangchi;Payam Heydari

引用次数: 0

Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure 物理时变传递函数作为通用的低开销功率- sca对策

IEEE open journal of circuits and systems Pub Date : 2023-08-04 DOI: 10.1109/OJCAS.2023.3302254

Archisman Ghosh;Debayan Das;Shreyas Sen

{"title":"Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure","authors":"Archisman Ghosh;Debayan Das;Shreyas Sen","doi":"10.1109/OJCAS.2023.3302254","DOIUrl":"10.1109/OJCAS.2023.3302254","url":null,"abstract":"Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show \u0000<inline-formula> <tex-math>$sim 5000times $ </tex-math></inline-formula>\u0000 minimum traces to disclosure (MTD) improvement over the unprotected implementation with \u0000<inline-formula> <tex-math>$sim 1.25times $ </tex-math></inline-formula>\u0000 power and \u0000<inline-formula> <tex-math>$sim 1.2times $ </tex-math></inline-formula>\u0000 area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows \u0000<inline-formula> <tex-math>$3.4M$ </tex-math></inline-formula>\u0000 MTD which is \u0000<inline-formula> <tex-math>$500times $ </tex-math></inline-formula>\u0000 greater than the unprotected solution.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"228-240"},"PeriodicalIF":0.0,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10208218.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43006579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices 用于植入式神经设备的混合磁电天线无线传感和能量采集的电路级建模与仿真。

IEEE open journal of circuits and systems Pub Date : 2023-03-20 DOI: 10.1109/OJCAS.2023.3259233

Diptashree Das;Ziyue Xu;Mehdi Nasrollahpour;Isabel Martos-Repath;Mohsen Zaeimbashi;Adam Khalifa;Ankit Mittal;Sydney S. Cash;Nian X. Sun;Aatmesh Shrivastava;Marvin Onabajo

{"title":"Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices","authors":"Diptashree Das;Ziyue Xu;Mehdi Nasrollahpour;Isabel Martos-Repath;Mohsen Zaeimbashi;Adam Khalifa;Ankit Mittal;Sydney S. Cash;Nian X. Sun;Aatmesh Shrivastava;Marvin Onabajo","doi":"10.1109/OJCAS.2023.3259233","DOIUrl":"10.1109/OJCAS.2023.3259233","url":null,"abstract":"A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"139-155"},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10076793","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41223293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

New Year Editorial 2023 2023年新年社论

IEEE open journal of circuits and systems Pub Date : 2023-03-01 DOI: 10.1109/OJCAS.2023.3245439

Gabriele Manganaro;Nicole Mcfarlane

引用次数: 0

Comprehensive Mapping of Continuous/Switching Circuits in CCM and DCM to Machine Learning Domain Using Homogeneous Graph Neural Networks 基于齐次图神经网络的CCM和DCM连续/开关电路到机器学习域的综合映射

IEEE open journal of circuits and systems Pub Date : 2023-01-04 DOI: 10.1109/OJCAS.2023.3234244

Ahmed K. Khamis;Mohammed Agamy

{"title":"Comprehensive Mapping of Continuous/Switching Circuits in CCM and DCM to Machine Learning Domain Using Homogeneous Graph Neural Networks","authors":"Ahmed K. Khamis;Mohammed Agamy","doi":"10.1109/OJCAS.2023.3234244","DOIUrl":"10.1109/OJCAS.2023.3234244","url":null,"abstract":"This paper proposes a method of transferring physical continuous and switching/converter circuits working in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) to graph representation, independent of the connection or the number of circuit components, so that machine learning (ML) algorithms and applications can be easily applied. Such methodology is generalized and is applicable to circuits with any number of switches, components, sources and loads, and can be useful in applications such as artificial intelligence (AI) based circuit design automation, layout optimization, circuit synthesis and performance monitoring and control. The proposed circuit representation and feature extraction methodology is applied to seven types of continuous circuits, ranging from second to fourth order and it is also applied to three of the most common converters (Buck, Boost, and Buck-boost) operating in CCM or DCM. A classifier ML task can easily differentiate between circuit types as well as their mode of operation, showing classification accuracy of 97.37% in continuous circuits and 100% in switching circuits.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"50-69"},"PeriodicalIF":0.0,"publicationDate":"2023-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10006651.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46165934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Instruction for Authors 作者须知

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3348971

引用次数: 0