IEEE open journal of circuits and systems最新文献

{"title":"Understanding Canadians' knowledge, attitudes and practices related to antimicrobial resistance and antibiotic use: Results from public opinion research.","authors":"Anna-Louise Crago, Stéphanie Alexandre, Kahina Abdesselam, Denise Gravel Tropper, Michael Hartmann, Glenys Smith, Tanya Lary","doi":"10.14745/ccdr.v48i1112a08","DOIUrl":"10.14745/ccdr.v48i1112a08","url":null,"abstract":"<p><strong>Background: </strong>Antimicrobial resistance is a current and pressing issue in Canada. Population-level antibiotic consumption is a key driver. The Public Health Agency of Canada undertook a comprehensive assessment of the Canadian public's knowledge, attitudes and practices in relation to antimicrobial resistance and antibiotic use, to help inform the implementation of public awareness and knowledge mobilization.</p><p><strong>Methods: </strong>Data were collected in three phases: 1) six in-person focus groups (53 participants) to help frame the survey; 2) nationwide survey administration to 1,515 Canadians 18 years and older via cell phone and landline; and 3) 12 online focus groups to analyze survey responses. Survey data is descriptive.</p><p><strong>Results: </strong>A third (33.9%) of survey respondents reported using antibiotics at least once in the previous 12 months, 15.8% more than twice and 4.6% more than five times. Antibiotic use was reported more among 1) those with a household income below $60,000, 2) those with a medical condition, 3) those without a university education and 4) among the youngest adults (18-24 years of age) and (25-34 years of age). Misinformation about antibiotics was common: 32.5% said antibiotics \"can kill viruses\"; 27.9% said they are \"effective against colds and flu\"; and 45.8% said they are \"effective in treating fungal infections\". Inaccurate information was reported more often by those 1) aged 18-24 years, 2) with a high school degree or less and 3) with a household income below $60,000. In focus groups, the time/money trade-offs involved in accessing medical care were reported to contribute to pushing for a prescription or using unprescribed antibiotics, particularly in more remote contexts, while the cost of a prescription contributed to sharing and using old antibiotics. A large majority, across all demographic groups, followed the advice of medical professionals in making health decisions.</p><p><strong>Conclusion: </strong>High trust in medical professionals presents an important opportunity for knowledge mobilization. Delayed prescriptions may alleviate concerns about the time/money constraints of accessing future care. Consideration should be given to prioritizing access to appropriate diagnostic and other technology for northern and/or remote communities and/or medical settings serving many young children to alleviate concerns of needing a prescription or of needing to return later.</p>","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"1 1","pages":"550-558"},"PeriodicalIF":0.0,"publicationDate":"2022-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10779429/pdf/","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84881415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wang Algebra: From Theory to Practice","authors":"Bob Ross;Cong Ling","doi":"10.1109/OJCAS.2022.3217065","DOIUrl":"10.1109/OJCAS.2022.3217065","url":null,"abstract":"Wang algebra was initiated by Ki-Tung Wang as a short-cut method for the analysis of electrical networks. It was later popularized by Duffin and has since found numerous applications in electrical engineering and graph theory. This is a semi-tutorial paper on Wang algebra, its history, and modern applications. We expand Duffin’s historic notes on Wang algebra to give a full account of Ki-Tung Wang’s life. A short proof of Wang algebra using group theory is presented. We exemplify the usefulness of Wang algebra in the design of T-coils. Bridged T-coils give a significant advantage in bandwidth, and were widely adopted in Tektronix oscilloscopes, but design details were guarded as a trade secret. The derivation presented in this paper, based on Wang algebra, is more general and simpler than those reported in literature. This novel derivation has not been shared with the public before.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"274-285"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/9684754/09930827.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41881318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System","authors":"Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone","doi":"10.1109/OJCAS.2022.3211844","DOIUrl":"10.1109/OJCAS.2022.3211844","url":null,"abstract":"This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller–Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE) are evaluated from a phase detector performance perspective to enable high CDR loop bandwidth. The impact of loop latency on the timing recovery of ADC-based PAM-4 receivers is also analyzed and demonstrated using accurate behavioral simulations. The analysis and behavioral results show that, to achieve high CDR loop bandwidth with a good jitter tolerance, the phase detector gain to noise ratio should be maximized, and CDR loop latency should be minimized.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"216-227"},"PeriodicalIF":0.0,"publicationDate":"2022-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9910561","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62854461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications","authors":"Li-Wei Liu;Yen-Chin Liao;Hsie-Chia Chang","doi":"10.1109/OJCAS.2022.3209152","DOIUrl":"10.1109/OJCAS.2022.3209152","url":null,"abstract":"An error floor phenomenon, decoding performance, and throughput are three major concerns for LDPC decoders in NAND Flash applications. With a penalty method and an active iteration mechanism, we present a Unified Penalty Gradient Descent Bit Flipping (UP-GDBF) decoding algorithm, which not only possesses error-floor free property but also improves convergence speed in decoding performance. To fulfill the high-throughput requirement while maintaining reliable error correction capability, we propose an energy-based backtracking scheme to reduce 40% latency with a negligible 0.8% area overhead. Implemented in TSMC 16nm process, the proposed 4KB LDPC decoder can achieve a throughput of 19.3 Gbps with 0.120 mm2 area to satisfy ONFI 5.0 throughput requirement. Compared to existing approaches, our decoder architecture provides superior data rate and decoding performance in both 1KB and 4KB LDPC codes.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"228-236"},"PeriodicalIF":0.0,"publicationDate":"2022-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9902993","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstrating Analog Inference on the BrainScaleS-2 Mobile System","authors":"Yannik Stradmann;Sebastian Billaudelle;Oliver Breitwieser;Falk Leonard Ebert;Arne Emmel;Dan Husmann;Joscha Ilmberger;Eric Müller;Philipp Spilger;Johannes Weis;Johannes Schemmel","doi":"10.1109/OJCAS.2022.3208413","DOIUrl":"10.1109/OJCAS.2022.3208413","url":null,"abstract":"We present the BrainScaleS-2 mobile system as a compact analog inference engine based on the BrainScaleS-2 ASIC and demonstrate its capabilities at classifying a medical electrocardiogram dataset. The analog network core of the ASIC is utilized to perform the multiply-accumulate operations of a convolutional deep neural network. At a system power consumption of 5.6W, we measure a total energy consumption of \u0000<inline-formula> <tex-math>$mathrm {192 ~mu text {J} }$ </tex-math></inline-formula>\u0000 for the ASIC and achieve a classification time of 276 \u0000<inline-formula> <tex-math>$mu$ </tex-math></inline-formula>\u0000s per electrocardiographic patient sample. Patients with atrial fibrillation are correctly identified with a detection rate of (93.7 ± 0.7)% at (14.0 ± 1.0)% false positives. The system is directly applicable to edge inference applications due to its small size, power envelope, and flexible I/O capabilities. It has enabled the BrainScaleS-2 ASIC to be operated reliably outside a specialized lab setting. In future applications, the system allows for a combination of conventional machine learning layers with online learning in spiking neural networks on a single neuromorphic platform.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"252-262"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/9684754/09896927.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43738811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SEKV-E: Parameter Extractor of Simplified EKV I-V Model for Low-Power Analog Circuits","authors":"Hung-Chi Han;Antonio D’Amico;Christian Enz","doi":"10.1109/OJCAS.2022.3179046","DOIUrl":"10.1109/OJCAS.2022.3179046","url":null,"abstract":"This paper presents the open-source Python-based parameter extractor (SEKV-E) for the simplified EKV (sEKV) model, which enables the modern low-power circuit designs with the inversion coefficient design methodology. The tool extracts the essential sEKV parameters automatically from the given \u0000<inline-formula> <tex-math>$I$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>$V$ </tex-math></inline-formula>\u0000 curves using the direct extraction and the multi-stage optimization process. It also handles the overfitting issue because of non-linear least squares. Moreover, this work demonstrates the SEKV-E as a universal tool by widely applying it to different silicon technologies, temperatures, dimensions, and back-gate voltages.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"162-167"},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896232","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems","authors":"Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar","doi":"10.1109/OJCAS.2022.3207598","DOIUrl":"10.1109/OJCAS.2022.3207598","url":null,"abstract":"Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named \u0000<inline-formula> <tex-math>${mathbf {L}}ife-time ,,{mathbf {P}}eak ,,{mathbf {P}}{ower~management~in},,{mathbf {M}}{ixed}-{mathbf {C}}{riticality,, systems}$ </tex-math></inline-formula>\u0000 (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"199-215"},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896164","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022","authors":"Alison Burdett","doi":"10.1109/OJCAS.2022.3202588","DOIUrl":"10.1109/OJCAS.2022.3202588","url":null,"abstract":"The International Symposium on Integrated Circuits and Systems (ISICAS) is a forum for dissemination of original work with experimental results from integrated circuits and systems in the areas of analog, digital, power, energy, biomedical, sensor interfaces and communications. Papers accepted to be presented at the symposium are automatically published in special issues of leading IEEE Circuits and Systems Society (CASS) journals, namely Transactions on Circuits and Systems (TCAS) Parts I and II, Transactions on Biomedical Circuits and Systems (TBioCAS), and Open Journal of Circuits and Systems (OJCAS).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"160-161"},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896231","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72854014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional Neural Networks","authors":"Jinho Yi;Jiachen Xu;Ethan Chen;Maysamreza Chamanzar;Vanessa Chen","doi":"10.1109/OJCAS.2022.3184302","DOIUrl":"10.1109/OJCAS.2022.3184302","url":null,"abstract":"Real-time in-sensor spike sorting is a forefront requirement in the development of brainmachine interfaces (BMIs). This work presents the characterization, design, and efficient implementation on a field-programmable gate array (FPGA) of a novel approach to neural spike sorting intended for implantable devices based on convolutional neural networks (CNNs). While the temporal features, the shape of the spike signals, could be highly mitigated from the ambient noise, the proposed classifier effectively extracts spatial features from the multi-channel neural signal to maintain high accuracy on the noisy data. The proposed classifier mechanism was tested on real data that is recorded from multi-channel electrodes, containing 27 neural units, and the classifier achieves 93.1% accuracy despite high temporal noise in the signal. For hardware synthesis, the CNN weights are quantized to reduce the model storage requirement by 93% compared to its floating point-precision version, and the model achieves an accuracy of 86.1%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"168-179"},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896230","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Resistor-Less nW-Level Bandgap Reference With Fine-Grained Voltage and Temperature Coefficient Trims","authors":"Ori Bass;Asaf Feldman;Joseph Shor","doi":"10.1109/OJCAS.2022.3206326","DOIUrl":"10.1109/OJCAS.2022.3206326","url":null,"abstract":"A nW-level BJT-based bandgap reference with fine grained voltage and temperature coefficient trimming is presented. The bandgap reference utilizes switched capacitors (SC) as impedance elements instead of resistors in a current mode configuration. This configuration enabled low power (38nW) with a minimal area (0.0174 mm2). The voltage could be trimmed independently without affecting the temperature coefficient. The SC’s are stacked in order to achieve accurate trimming without using unrealistically small capacitors. The temperature coefficient can be trimmed between 50-200 ppm/°C in either direction, while the voltage can be trimmed between 580-800mV.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"192-198"},"PeriodicalIF":0.0,"publicationDate":"2022-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9888150","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}