IEEE open journal of circuits and systems最新文献_第10页

SEKV-E: Parameter Extractor of Simplified EKV I-V Model for Low-Power Analog Circuits SEKV-E:用于低功耗模拟电路的简化EKV I-V模型的参数提取器

IEEE open journal of circuits and systems Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3179046

Hung-Chi Han;Antonio D’Amico;Christian Enz

引用次数: 2

Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems 容错混合临界系统的峰值功率感知全寿命可靠性改进

IEEE open journal of circuits and systems Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3207598

Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar

{"title":"Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems","authors":"Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar","doi":"10.1109/OJCAS.2022.3207598","DOIUrl":"10.1109/OJCAS.2022.3207598","url":null,"abstract":"Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named \u0000<inline-formula> <tex-math>${mathbf {L}}ife-time ,,{mathbf {P}}eak ,,{mathbf {P}}{ower~management~in},,{mathbf {M}}{ixed}-{mathbf {C}}{riticality,, systems}$ </tex-math></inline-formula>\u0000 (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"199-215"},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896164","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022 IEEE电路与系统开放杂志:ISICAS 2022特别部分

IEEE open journal of circuits and systems Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3202588

Alison Burdett

引用次数: 0

Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional Neural Networks 基于卷积神经网络的多通道多类实时神经脉冲排序

IEEE open journal of circuits and systems Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3184302

Jinho Yi;Jiachen Xu;Ethan Chen;Maysamreza Chamanzar;Vanessa Chen

引用次数: 0

A Resistor-Less nW-Level Bandgap Reference With Fine-Grained Voltage and Temperature Coefficient Trims 具有细粒度电压和温度系数的无电阻nw级带隙基准

IEEE open journal of circuits and systems Pub Date : 2022-09-13 DOI: 10.1109/OJCAS.2022.3206326

Ori Bass;Asaf Feldman;Joseph Shor

引用次数: 1

A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories 用于nand闪存的38.64 gb /s大cpm 2kb LDPC解码器实现

IEEE open journal of circuits and systems Pub Date : 2022-09-01 DOI: 10.1109/OJCAS.2022.3203849

Li-Wei Liu;Mu-Hua Yuan;Yen-Chin Liao;Hsie-Chia Chang

引用次数: 0

An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications 用于高速有线应用的高效滤波器组多载波系统

IEEE open journal of circuits and systems Pub Date : 2022-08-09 DOI: 10.1109/OJCAS.2022.3197333

Jeremy Cosson-Martin;Hossein Shakiba;Ali Sheikholeslami

{"title":"An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications","authors":"Jeremy Cosson-Martin;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2022.3197333","DOIUrl":"10.1109/OJCAS.2022.3197333","url":null,"abstract":"This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a \u0000<inline-formula> <tex-math>$35dB$ </tex-math></inline-formula>\u0000 channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"147-159"},"PeriodicalIF":0.0,"publicationDate":"2022-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9852766","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications 高速有线通信单线ofdm串行链路的设计空间探索

IEEE open journal of circuits and systems Pub Date : 2022-07-12 DOI: 10.1109/OJCAS.2022.3189550

Gain Kim

{"title":"Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications","authors":"Gain Kim","doi":"10.1109/OJCAS.2022.3189550","DOIUrl":"10.1109/OJCAS.2022.3189550","url":null,"abstract":"The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"134-146"},"PeriodicalIF":0.0,"publicationDate":"2022-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9827577","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analysis and Design Methodology of RF Energy Harvesting Rectifier Circuit for Ultra-Low Power Applications 超低功耗射频能量收集整流电路的分析与设计方法

IEEE open journal of circuits and systems Pub Date : 2022-04-21 DOI: 10.1109/OJCAS.2022.3169437

Ziyue Xu;Adam Khalifa;Ankit Mittal;Mehdi Nasrollahpourmotlaghzanjani;Ralph Etienne-Cummings;Nian Xiang Sun;Sydney S. Cash;Aatmesh Shrivastava

{"title":"Analysis and Design Methodology of RF Energy Harvesting Rectifier Circuit for Ultra-Low Power Applications","authors":"Ziyue Xu;Adam Khalifa;Ankit Mittal;Mehdi Nasrollahpourmotlaghzanjani;Ralph Etienne-Cummings;Nian Xiang Sun;Sydney S. Cash;Aatmesh Shrivastava","doi":"10.1109/OJCAS.2022.3169437","DOIUrl":"10.1109/OJCAS.2022.3169437","url":null,"abstract":"This paper reviews and analyses the design of popular radio frequency energy harvesting systems and proposes a method to qualitatively and quantitatively analyze their circuit architectures using new square-wave approximation method. This approach helps in simplifying design analysis. Using this analysis, we can establish no load output voltage characteristics, upper limit on rectifier efficiency, and maximum power characteristics of a rectifier. This paper will help guide the design of RF energy harvesting rectifier circuits for radio frequency identification (RFIDs), the Internet of Things (IoTs), wearable, and implantable medical device applications. Different application scenarios are explained in the context of design challenges, and corresponding design considerations are discussed in order to evaluate their performance. The pros and cons of different rectifier topologies are also investigated. In addition to presenting the popular rectifier topologies, new measurement results of these energy harvester topologies, fabricated in 65nm, 130nm and 180nm CMOS technologies are also presented.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"82-96"},"PeriodicalIF":0.0,"publicationDate":"2022-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9761164","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46333264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier 一种基于逆变器的低噪声高增益宽带跨阻放大器

IEEE open journal of circuits and systems Pub Date : 2022-04-04 DOI: 10.1109/OJCAS.2022.3164396

Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami

{"title":"A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier","authors":"Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2022.3164396","DOIUrl":"10.1109/OJCAS.2022.3164396","url":null,"abstract":"In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm\u0000<sup>2</sup>\u0000.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"3 ","pages":"72-81"},"PeriodicalIF":0.0,"publicationDate":"2022-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9748875","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3