{"title":"An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process","authors":"Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2023.3236567","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3236567","url":null,"abstract":"In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dB $Omega $ , a BW of 14.8 GHz, an input-referred noise of 33.6 pA/ $surd $ Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consumes 49 mW and occupies an active area of 0.0076 mm 2.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"36-49"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10015890.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dong-Hyun Seo;Archisman Ghosh;Debayan Das;Mayukh Nath;Santosh Ghosh;Shreyas Sen
{"title":"PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing","authors":"Dong-Hyun Seo;Archisman Ghosh;Debayan Das;Mayukh Nath;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJCAS.2023.3292712","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3292712","url":null,"abstract":"This paper presents the design and analysis of a pro-active strategy to detect the presence of an electromagnetic (EM) side-channel analysis (SCA) attack, using Patterned-Ground co-planar Capacitive Asymmetry Sensing (PG-CAS) system. The PG-CAS system senses the asymmetry created in the plate-ground capacitance and turns on a SCA countermeasure in presence of an EM probe. The proposed PG-CAS system for approaching probe consists of the EM SCA detection sensor plate and circuits. The EM SCA detection sensor is implemented as a grid of four metal plates of the same dimensions using the top metal layer along with a patterned-ground plane at the immediate lower metal layer. The EM SCA detection system consists of a proximity to capacitance conversion circuit, digital synchronization logic circuit to detect and alarm the IC, and an EM SCA countermeasure. When an attack is detected, the countermeasure is turned on based on the deviation of the symmetry of the plate-ground capacitance pairs. The PG-CAS system-level post-layout simulation results using TSMC 65nm technology and Ansys Maxwell show a $>5times $ improvement in the detection range and a $sim 29times $ improvement in power consumption over existing inductive sensing methods for attack detection.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"271-282"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10192257.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a Non-Contact Human Sign Monitoring System Based on Microwave Sensors","authors":"雨泽 李","doi":"10.12677/ojcs.2023.122003","DOIUrl":"https://doi.org/10.12677/ojcs.2023.122003","url":null,"abstract":"In this paper","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"20 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87755717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2023 Index IEEE Open Journal of Circuits and Systems Vol. 4","authors":"","doi":"10.1109/OJCAS.2024.3356108","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3356108","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"363-369"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10410125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139504507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Research on Model Parameter Identification of Lithium Ion Battery","authors":"启煌 朱","doi":"10.12677/ojcs.2023.122002","DOIUrl":"https://doi.org/10.12677/ojcs.2023.122002","url":null,"abstract":"Due to the change in automobile working conditions, the structure coefficient of automobile power battery pack also appears to nonlinear change. In order to realize efficient control of such nonlinear battery components, this paper chooses the second-order RC model as the equivalent circuit model of the battery, and uses the constant current charge-discharge test of the battery, the calibra-朱启煌","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"44 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81867409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander
{"title":"Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers","authors":"Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander","doi":"10.1109/OJCAS.2022.3232638","DOIUrl":"https://doi.org/10.1109/OJCAS.2022.3232638","url":null,"abstract":"Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in <inline-formula> <tex-math notation=\"LaTeX\">$0.35 mu mathrm{m}$ </tex-math></inline-formula> CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape <inline-formula> <tex-math notation=\"LaTeX\">$Pleft(T_Eright)$ </tex-math></inline-formula> and yield loss <inline-formula> <tex-math notation=\"LaTeX\">$Pleft(Y_Lright)$ </tex-math></inline-formula> of <inline-formula> <tex-math notation=\"LaTeX\">$5 cdot 10^{-2}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$1.89 cdot 10^{-2}$ </tex-math></inline-formula> respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"70-84"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10002329.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An On-Chip Fully Connected Neural Network Training Hardware Accelerator Based on Brain Float Point and Sparsity Awareness","authors":"Tsung-Han Tsai;Ding-Bang Lin","doi":"10.1109/OJCAS.2023.3245061","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3245061","url":null,"abstract":"In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other applications, gradually replacing traditional algorithms. It shows that the rise of neural networks has led to the reform of artificial intelligence. Since neural network algorithms are computationally intensive, they require GPUs or accelerated hardware for real-time computation. However, the high cost and high power consumption of GPUs result in low energy efficiency. It recently led to much research on accelerated digital circuit hardware design for deep neural networks. In this paper, we propose an efficient and flexible neural network training processor for fully connected layers. Our proposed training processor features low power consumption, high throughput, and high energy efficiency. It uses the sparsity of neuron activations to reduce the number of memory accesses and memory space to achieve an efficient training accelerator. The proposed processor uses a novel reconfigurable computing architecture to maintain high performance when operating Forward Propagation and Backward Propagation. The processor is implemented in Xilinx Zynq UltraSacle+MPSoC ZCU104 FPGA, with an operating frequency of 200MHz and power consumption of 6.444W, and can achieve 102.43 GOPS.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"85-98"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10051716.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Polychronous Oscillatory Cellular Neural Networks for Solving Graph Coloring Problems","authors":"Richelle L. Smith;Thomas H. Lee","doi":"10.1109/OJCAS.2023.3262204","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3262204","url":null,"abstract":"This paper presents polychronous oscillatory cellular neural networks, designed for solving graph coloring problems. We propose to apply the Potts model to the four-coloring problem, using a network of locally connected oscillators under superharmonic injection locking. Based on our mapping of the Potts model to injection-locked oscillators, we utilize oscillators under divide-by-4 injection locking. Four possible states per oscillator are encoded in a polychronous fashion, where the steady state oscillator phases are analogous to the time-locked neuronal firing patterns of polychronous neurons. We apply impulse sensitivity function (ISF) theory to model and optimize the high-order injection locking of the oscillators. CMOS circuit design of a polychronous oscillatory neural network is presented, and coloring of a geographic map is demonstrated, with simulation results and design guidelines. There is good agreement between theory and Spectre simulation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"156-164"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10081435.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS","authors":"Liwen Lin;Ka-Meng Lei;Pui-In Mak;Rui P. Martins","doi":"10.1109/OJCAS.2023.3256368","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3256368","url":null,"abstract":"This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager <inline-formula> <tex-math notation=\"LaTeX\">$(mu $ </tex-math></inline-formula>PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such <inline-formula> <tex-math notation=\"LaTeX\">$mu $ </tex-math></inline-formula>PM shows a high power efficiency by introducing a 3-stage cascaded structure and a single voltage-regulation loop; they together uphold the performance of the XO-Timer amid supply-voltage and temperature variations. The core amplifier of the XO-Timer is ULV-enabled, and is reconfigurable (i.e., 1-stage and 3-stage gm) to balance between the power budget and performance under the high-performance mode (HPM) and low-power mode (LPM). Fabricated in 28-nm CMOS, the XO-Timer in HPM generates a 16-MHz clock with a power of <inline-formula> <tex-math notation=\"LaTeX\">$24.3 ~mu text{W}$ </tex-math></inline-formula>, and a phase noise of −133.8 dBc/Hz at 1-kHz offset, resulting in a Figure-of-Merit (FoM1) of −236 dBc/Hz. In the LPM, the XO-Timer delivers a 32.258-kHz clock while consuming <inline-formula> <tex-math notation=\"LaTeX\">$11.4 ~mu text{W}$ </tex-math></inline-formula>. The sleep-timer FoM2 is <inline-formula> <tex-math notation=\"LaTeX\">$14.8 ~mu text{W}$ </tex-math></inline-formula> and the Allan deviation is 35.1 ppb, achieving the lowest supply voltage (0.25 V) not only for a dual-mode XO-Timer but also for a MHz-range XO.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"126-138"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10068768.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Deep Reinforcement Learning on FPGA for Self-Healing Cryogenic Power Amplifier Control","authors":"Jiachen Xu;Yuyi Shen;Jinho Yi;Ethan Chen;Vanessa Chen","doi":"10.1109/OJCAS.2023.3282929","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3282929","url":null,"abstract":"Wireless sensing and communication for space exploration in areas inaccessible to human often suffer from severe performance degradation due to the cryogenic effects on the transmitters’ circuits. To survive extreme temperatures, programmable radio frequency (RF) power amplifiers (PA) can be built into the transmitter, and intelligent PA controllers need to be integrated into the system to interact with the environment and restore the PA’s functionalities. This problem can be modeled as the controller acts (control the PA) in an environment to maximize the reward (signal quality), and it is most suitable to use reinforcement learning as a solution. This paper presents a cryogenic and energy-efficient reinforcement learning (RL) module on Field Programmable Gate Arrays (FPGA) that can directly program the PA. By characterizing a self-healing PA in a liquid nitrogen environment, we generated an RF signal data set and built an interactive RL environment to model the PA’s behaviors across its configurations and cryogenic temperatures down to −197°C. We developed a deep RL model with a high generalization capability introduced by the neural networks to control the PA and restore its performance. The RL model with fixed-point training and inference is implemented on FPGA to survive the cryogenic conditions and carry out fast and low-power training and inference for PA control. All functionalities of the programmed FPGA operate correctly in the cryogenic testing environment.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"176-187"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10143969.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}