IEEE open journal of circuits and systems最新文献

Performance Prediction of Incremental ΔΣ ADCs 增量式ΔΣ adc的性能预测

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-09-05 DOI: 10.1109/OJCAS.2025.3606618

Paul Kaesser;Maurits Ortmanns

引用次数: 0

A Low-Loss T/R Module With Balanced Power Amplifier for High Antenna Impedance Tolerance 具有高天线阻抗容限的平衡功率放大器的低损耗收发模块

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-09-03 DOI: 10.1109/OJCAS.2025.3604902

Uday Maurya;Mahima Arrawatia;Nagarjuna Nallam

引用次数: 0

Prediction-Based Spectrum Sensing Framework for Cognitive Radio 基于预测的认知无线电频谱感知框架

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-27 DOI: 10.1109/OJCAS.2025.3592376

Andres Rojas;Gawen Follet;Gordana Jovanovic Dolecek;José M. De La Rosa;Gustavo Liñán-Cembrano

{"title":"Prediction-Based Spectrum Sensing Framework for Cognitive Radio","authors":"Andres Rojas;Gawen Follet;Gordana Jovanovic Dolecek;José M. De La Rosa;Gustavo Liñán-Cembrano","doi":"10.1109/OJCAS.2025.3592376","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3592376","url":null,"abstract":"This paper presents a hardware-software deep learning architecture for prediction-based spectrum sensing in Cognitive Radio (CR) applications. A convolutional neural network-based predictor for spectrum occupancy was trained using the band power from I/Q samples acquired by a softwaredefined radio (SDR). Additionally, a second neural engine was trained for radio frequency (RF) frame detection based on spectrograms. We implemented a transfer-learning solution using a You-Only-LookOnce version 8 nano model with a synthetic dataset comprising thousands of wireless signals, including Wi-Fi, Bluetooth, and collision frames. Once trained, the two neural networks were transferred to a Raspberry Pi 5 – an affordable single-board computer – connected to two (one for Rx, one for Tx) ADALM-PLUTO SDR systems for benchmarking using over-the-air signals in the 2.4 GHz band. Together with our methodology and experimental results, the paper also presents an overview of current spectrum prediction proposals and RF frame detectors. Remarkably, to the best of our knowledge, this proposed framework is the first approach towards an Internet of Things-suitable implementation of prediction-based spectrum sensing for CR applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"313-328"},"PeriodicalIF":2.4,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142737","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving Neural Network Fault Tolerance Against Weight Attack 改进神经网络对权重攻击的容错性

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-26 DOI: 10.1109/OJCAS.2025.3602678

Chia Jen Cheng;Ethan Chen;Vanessa Chen

引用次数: 0

A Proxy ADC Framework for Side-Channel Secure ADC Analysis 一种用于侧信道安全ADC分析的代理ADC框架

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-25 DOI: 10.1109/OJCAS.2025.3602353

Andrew Ash;John Hu

{"title":"A Proxy ADC Framework for Side-Channel Secure ADC Analysis","authors":"Andrew Ash;John Hu","doi":"10.1109/OJCAS.2025.3602353","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3602353","url":null,"abstract":"In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"401-413"},"PeriodicalIF":2.4,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11138015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A High Efficient Cross-Coupled Active Rectifier by Using High Speed Switching Comparators for Wireless Power Receiver 基于高速开关比较器的无线电源接收机高效交叉耦合有源整流器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-14 DOI: 10.1109/OJCAS.2025.3598990

Syed Adil Ali Shah;Young-Gun Pu;Young-Joon Kim;Kang-Yoon Lee

{"title":"A High Efficient Cross-Coupled Active Rectifier by Using High Speed Switching Comparators for Wireless Power Receiver","authors":"Syed Adil Ali Shah;Young-Gun Pu;Young-Joon Kim;Kang-Yoon Lee","doi":"10.1109/OJCAS.2025.3598990","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3598990","url":null,"abstract":"This paper introduces a highly efficient cross-coupled active rectifier with fast switching comparators for wireless power transfer (WPT) system. Wireless power transfer technology is increasingly being utilized in various applications. In our proposed design an active diode switches are introduced at lower side of power MOSFET to minimize the switching delay in power transistors and also reduces reverse leakage current to boost power conversion efficiency. The active diode is constructed from high-speed comparators and CMOS power switches. A cross-coupled technique is applied to the high side PMOS power transistors, in order to minimizing power consumption and optimizing current management. This enhancement not only improves the power efficiency of the cross-coupled active rectifier but also prolongs battery life and boosts the overall Efficiency. The cross-coupled architecture of the proposed rectifier enables high-speed switching, which is necessary for its design. This allows for fast response times and efficient signal processing. The presented cross-coupled active rectifier is designed using <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS technology. It delivers 2.77 W of output power using a <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>F capacitor with a 0.3A load current, and it achieves a power efficiency of 92.4%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"393-400"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Review on Sub-0.21-V Ultra-Low-Supply-Voltage Analog-to-Digital Converters sub -0.21 v超低电源电压模数转换器研究进展

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-01 DOI: 10.1109/OJCAS.2025.3574336

Eric Christie;Jared Marchant;Shea Smith;Long Kong;Chia-Hung Chen;Shiuh-Hua Wood Chiang

引用次数: 0

Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC 用于SAR ADC时钟生成的亚阈值全数字DLL

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-01 DOI: 10.1109/OJCAS.2025.3586748

Wenhao Wu;Fei Yuan;Yushi Zhou

{"title":"Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC","authors":"Wenhao Wu;Fei Yuan;Yushi Zhou","doi":"10.1109/OJCAS.2025.3586748","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3586748","url":null,"abstract":"This paper presents a sub-threshold all-digital delay-locked loop (DLL) for the generation of the timing signals of low-power low-data-rate successive approximation register analog-to-digital converters. The delay line of the DLL consists of a set of cascaded static inverters with its large per-stage-delay obtained by powering the delay with an exceedingly low supply voltage. The per-stage-delay of the delay line is adjusted by varying the supply voltage provided by a sub-threshold voltage generator. Voltage recovery blocks consisting of cascaded static inverters with different supply voltages are used to recover the low voltage swing of the delay line to the nominal voltage swing of the DLL. High-voltage-threshold pMOS transistors are used to minimize the short-circuit-induced power consumption of voltage-recovering inverters. The proposed DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3v3 device models. Simulation results show the DLL locks to a <inline-formula> <tex-math>$0sim 0.6$ </tex-math></inline-formula> V 100 kHz 50% duty cycle external timing reference at FF/0.6V/-<inline-formula> <tex-math>$20^{o}$ </tex-math></inline-formula>C, TT/0.6V/<inline-formula> <tex-math>$27^{o}$ </tex-math></inline-formula>C, and SS/0.6V/<inline-formula> <tex-math>$60^{o}$ </tex-math></inline-formula>C in approximately 7 cycles of the timing reference with no accumulated static phase errors. The DLL occupies an area of 0.00559 mm2, offers 0.35% normalized root-mean-square jitter, and consumes 92 nW.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"270-282"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106517","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison and Design of Linear and Exponential Integrated Charge Pumps 线性和指数集成电荷泵的比较与设计

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-01 DOI: 10.1109/OJCAS.2025.3583268

Masoud Askariraad;Stefano Gregori

{"title":"Comparison and Design of Linear and Exponential Integrated Charge Pumps","authors":"Masoud Askariraad;Stefano Gregori","doi":"10.1109/OJCAS.2025.3583268","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3583268","url":null,"abstract":"This paper presents static and dynamic models for linear and exponential integrated charge pumps in both step-up and step-down modes. The static models are used to compare the slow-switching and fast-switching output resistance of various configurations, considering optimized and non-optimized capacitors and switches. In the dynamic models, the self-loading capacitance is determined using a simpler approach than previous works, allowing for a more straightforward comparison of the start-up time and charging efficiency. To highlight the differences between linear and exponential charge pumps, the working voltages of capacitors and switches are calculated, with these expressions guiding the selection of the most appropriate devices for each configuration. Additionally, parasitic capacitances and leakage currents are modeled and analyzed across the circuit configurations, and their impact on overall efficiency is assessed. The procedure for optimally sizing capacitors and switches using different device types is then discussed. Finally, two design examples in 65-nm CMOS technology are presented to validate the models, demonstrate design procedures, and highlight the advantages and limitations of practical implementations of each circuit.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"295-312"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106932","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC 低功耗逐次逼近ADC动态比较器的比较研究

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-08-01 DOI: 10.1109/OJCAS.2025.3565921

Fei Yuan

{"title":"A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC","authors":"Fei Yuan","doi":"10.1109/OJCAS.2025.3565921","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3565921","url":null,"abstract":"This paper provides a critical review and the classification of comparators in low-power low-data-rate (1 kS/s~1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs). Both voltage-domain and time-domain comparators are studied and their pros and cons are examined. The architecture, comparison time, and power consumption of five widely used voltage-domain dynamic comparators are studied first. It is followed with an investigation of kickback in comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converters (DACs) of SAR ADCs arising from the different resistances of DAC switches gives rise to a differential clock kickback that occurs earlier than output kickback with more strength hence dictating kickback in dynamic comparators. If the strength and duration of clock kickback are sufficiently large, the comparator will yield an erroneous output. The dependence of clock kickback on the input of SAR ADCs in the least significant bit (LSB) conversion is also investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are investigated, and the minimum tuning bits of digitally tuned offset compensation capacitor arrays is obtained. The noise of dynamic comparators is also investigated and design trade-offs between noise, power consumption, kickback, and the loading of the comparator on DAC are examined. The extensive simulation results of the comparators designed in a TSMC 130 nm 1.2 V CMOS technologies with reduced supply voltages and analyzed using Spectre from Cadence Design Systems with BSIM 3.3 device models are provided.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"241-256"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0