IEEE open journal of circuits and systems最新文献

Non-Iterative Square-Wave Modeling of Multistage CMOS Dickson Rectifiers for RF Energy Harvesting 用于射频能量收集的多级CMOS Dickson整流器的非迭代方波建模

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-20 DOI: 10.1109/OJCAS.2026.3666784

Utkarsh Kumar;Ankit Mittal;Ufuk Muncuk;Aatmesh Shrivastava

{"title":"Non-Iterative Square-Wave Modeling of Multistage CMOS Dickson Rectifiers for RF Energy Harvesting","authors":"Utkarsh Kumar;Ankit Mittal;Ufuk Muncuk;Aatmesh Shrivastava","doi":"10.1109/OJCAS.2026.3666784","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3666784","url":null,"abstract":"Performance evaluation of UHF RF energy harvesters is limited by the complexity of analyzing rectifiers under sinusoidal excitation. This work presents a non-iterative square-wave-based analytical method for modeling multistage CMOS Dickson rectifiers. Closed-form expressions for output voltage, output power, and power conversion efficiency (PCE) are derived using a fixed-amplitude scaling factor (<inline-formula> <tex-math>$K$ </tex-math></inline-formula> = <inline-formula> <tex-math>$pi /4$ </tex-math></inline-formula>). The approach is validated through post-layout simulations and measurements in 65-nm CMOS at 2.4 GHz. Simulated and modeled output power deviations are 2.19%, 2.09%, and 2.67% for single-, three-, and six-stage rectifiers, respectively, with output voltage and PCE deviations below 3.10% across input power and load conditions. The model is further evaluated from 0.5 to 3 GHz and across process corners. A fabricated three-stage prototype (<inline-formula> <tex-math>$86~mu mathrm {m} times 60~mu mathrm {m}$ </tex-math></inline-formula>) achieves a peak PCE of 57.94%, a power dynamic range (PDR) of 22 dB, and a sensitivity of −23.5 dBm at <inline-formula> <tex-math>$V_{mathrm {OUT}}$ </tex-math></inline-formula> = 1 V. Measured results show deviations of 2.85% in PCE and 2.74% in output power from simulation, confirming the accuracy of the proposed square-wave analytical model.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"82-94"},"PeriodicalIF":2.4,"publicationDate":"2026-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11404138","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analog Convolution Circuit System Implemented With Capacitor Array Superposition 用电容阵列叠加实现模拟卷积电路系统

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-12 DOI: 10.1109/OJCAS.2026.3664009

Chung-Yi Wang;Ping-Hsuan Hsieh;Zi-Cin Wang

引用次数: 0

A Miniaturized Ingestible Capsule With Integrated ASIC for Energy-Efficient Sensing in the Gastrointestinal Tract 用于胃肠道节能传感的集成ASIC的小型化可消化胶囊

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-12 DOI: 10.1109/OJCAS.2026.3664175

Ramzy Rammouz;Vasileios Adamopoulos;Ivan D. Castro Miller;Wim Sijbers;Ria Sijabat;Dimitrios Firfilionis;Qiuyang Lin;Benjamin Calmé;Tom Torfs

引用次数: 0

A SAR-Assisted Continuous-Time M-0 MASH Delta-Sigma Modulator With Digital-Domain Noise Leakage Shaping sar辅助连续时间M-0 MASH δ - σ调制器与数字域噪声泄漏整形

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-10 DOI: 10.1109/OJCAS.2026.3663446

Kent Edrian Lozada;Bo Gao;Raymond Mabilangan;Charlie Tahar;Kun-Woo Park;Young-Hun Moon;Kwan-Hoon Song;Seung-Tak Ryu

{"title":"A SAR-Assisted Continuous-Time M-0 MASH Delta-Sigma Modulator With Digital-Domain Noise Leakage Shaping","authors":"Kent Edrian Lozada;Bo Gao;Raymond Mabilangan;Charlie Tahar;Kun-Woo Park;Young-Hun Moon;Kwan-Hoon Song;Seung-Tak Ryu","doi":"10.1109/OJCAS.2026.3663446","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3663446","url":null,"abstract":"Delta–sigma (<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>) modulators are widely used in high-resolution analog-to-digital converters (ADCs). With continued technology scaling, digital-intensive <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> architectures are increasingly favored over traditional analog-centric designs. This work presents a successive approximation register (SAR)-assisted digital noise-coupling (DNC)-based noise-leakage shaping technique for continuous-time (CT) <inline-formula> <tex-math>$M$ </tex-math></inline-formula>–0 multi-stage noise-shaping (MASH) <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> modulators, complemented by a digital back-end integrator. The key building blocks for implementing DNC-based noise-leakage shaping, including the interface between the first and second stages, are efficiently realized through a SAR-assisted structure, while the DNC filter is implemented using simple digital delay cells, enabling a compact and hardware-efficient design. Extensive behavioral simulations demonstrate robustness against key nonidealities, including finite opamp gain, limited unity-gain bandwidth (UGBW), and wide coefficient variations, and circuit-level results validate the practicality and effectiveness of the proposed architecture for high-resolution, low-power applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"69-81"},"PeriodicalIF":2.4,"publicationDate":"2026-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11390665","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147299653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal-Aware NoC for AI Computing: Tools, Algorithms, and Applications 人工智能计算的热感知NoC：工具、算法和应用

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-09 DOI: 10.1109/OJCAS.2026.3662252

Fakhrul Zaman Rokhani;Mircea R. Stan;Maurizio Palesi;Kun-Chih Chen

{"title":"Thermal-Aware NoC for AI Computing: Tools, Algorithms, and Applications","authors":"Fakhrul Zaman Rokhani;Mircea R. Stan;Maurizio Palesi;Kun-Chih Chen","doi":"10.1109/OJCAS.2026.3662252","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3662252","url":null,"abstract":"The explosive growth of AI workloads elevates on-chip communication and heat dissipation to first-order constraints. This survey paper consolidates thermal-aware Network-on-Chip (NoC) design for AI computing across tools, algorithms, and applications. Concretely, we first assemble a reproducible toolchain that couples cycle-accurate NoC simulators with power/thermal solvers and machine-learning surrogates for fast temperature prediction. We then structure the design space along three design dimensions: sensing strategies, control methodologies, and thermal- and traffic-aware data delivery. Finally, we close the loop among traffic, power, and temperature via an integrated co-simulation workflow, providing practical guidelines for thermal-aware NoC-based AI accelerator designs. Unlike general DNN-accelerator surveys, this survey paper focuses on the thermal–NoC interplay under realistic AI workloads and provides an actionable, closed-loop methodology and tooling for scalable, verifiable evaluation. We conclude with open challenges, scalable yet faithful co-simulation, standardized traces/interfaces, packaging-aware models, and uncertainty-aware surrogates, to guide the path toward thermally resilient, high-throughput AI systems.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"43-59"},"PeriodicalIF":2.4,"publicationDate":"2026-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11381451","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Equalization and Coding Techniques for Edge Modulation Signaling 边缘调制信令的均衡和编码技术

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-06 DOI: 10.1109/OJCAS.2026.3661924

Richelle L. Smith;Shakib Mahmood;Carl W. Werner;Thomas H. Lee;Masum Hossain

引用次数: 0

A High Gain Operational Amplifier With Dual-Tail Source Architecture for Fast Slewing 一种用于快速回转的高增益双尾源结构运算放大器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-02-02 DOI: 10.1109/OJCAS.2026.3659945

Meysam Akbari;Zahra Hashemi;Erika Covi;Kea-Tiong Tang

{"title":"A High Gain Operational Amplifier With Dual-Tail Source Architecture for Fast Slewing","authors":"Meysam Akbari;Zahra Hashemi;Erika Covi;Kea-Tiong Tang","doi":"10.1109/OJCAS.2026.3659945","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3659945","url":null,"abstract":"This work introduces an enhanced operational amplifier architecture in which four flipped voltage follower (FVF) cells act as adaptive tail current sources to improve the performance of a conventional current mirror (CM)-based design. The FVF cells dynamically boost the differential pair current beyond the nominal bias level during the slewing interval, enabling a significantly higher slew rate and reduced settling time. By employing both n-channel and p-channel input stages driving cascode loads, the proposed dual FVF-controlled tail sources improve efficiency for both small- and large-signal operations. Additionally, the use of supplementary input devices increases the overall transconductance, thereby achieving higher DC gain and extended gain–bandwidth product. The amplifier was implemented in TSMC 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology and validated through measurements, demonstrating a DC gain of 73.3 dB, a unity-gain bandwidth of 98.4 MHz, and a slew rate of 102.7 V/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s. The circuit operates from a 1.8-V supply, driving a 16-pF capacitive load, with a power consumption of <inline-formula> <tex-math>$642~mu $ </tex-math></inline-formula>W.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"11-20"},"PeriodicalIF":2.4,"publicationDate":"2026-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11370417","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask 使用单个光掩模的可编程DNN处理器的连接感知

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-23 DOI: 10.1109/OJCAS.2026.3656510

Jaewon Shin;Mototsugu Hamada;Atsutake Kosuge

{"title":"A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask","authors":"Jaewon Shin;Mototsugu Hamada;Atsutake Kosuge","doi":"10.1109/OJCAS.2026.3656510","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3656510","url":null,"abstract":"This paper presents a via-programmable DNN processor architecture, the Via-Programmable Neuron Array (VPNA), designed for low-NRE and low-power AIoT applications. To enable shared base-chip layouts across diverse workloads, a connectivity-aware design ensures tile-to-tile routing under a column-wise placement rule. A <inline-formula> <tex-math>$6{times }6$ </tex-math></inline-formula> programmable-wire structure supports task-specific data paths, and via-based ternary-weight mapping allows multiple tasks to reuse the same base chip with a single via mask. A unified bit-serial neuron circuit supports convolution and pooling operations under both neuron-serial and neuron-parallel modes, completing the functional implementation required for one-dimensional time-series DNNs. Post-layout evaluations in a 40 nm CMOS process demonstrate sub-milliwatt power consumption and sufficient inference accuracy across representative AIoT tasks, including keyword spotting, ECG arrhythmia detection, and EEG seizure detection. Compared with prior FPGA- and ASIC-based accelerators, the proposed architecture achieves a better trade-off among low power, low NRE cost, and task-level flexibility, highlighting its potential as a scalable foundation for future ultra-low-NRE and field-programmable AIoT processors.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"11-20"},"PeriodicalIF":2.4,"publicationDate":"2026-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11362923","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2025 Index IEEE Open Journal of Circuits and Systems 电路与系统开放杂志

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-21 DOI: 10.1109/OJCAS.2026.3657028

引用次数: 0

Spur Analysis and Linearity Enhancement in Fractional-N Phase Locked Loops Through Parallel Sigma–Delta Modulators With Time Offsets 通过带时间偏移的并行Sigma-Delta调制器对分数n锁相环的杂散分析和线性增强

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-19 DOI: 10.1109/OJCAS.2026.3655136

Johan Holmstedt;Henrik Sjöland

{"title":"Spur Analysis and Linearity Enhancement in Fractional-N Phase Locked Loops Through Parallel Sigma–Delta Modulators With Time Offsets","authors":"Johan Holmstedt;Henrik Sjöland","doi":"10.1109/OJCAS.2026.3655136","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3655136","url":null,"abstract":"This article presents a theoretical framework for deriving simple analytical expressions for spurs resulting from second and third order nonlinearities in fractional-N phase locked loops (PLL). Furthermore, a previously proposed linearization technique where several sigma-delta modulators (SDMs) operate in parallel with relative time offsets between them, is further analyzed using the periodic nonlinearity noise (PNN) framework. Closed form expressions are derived for the spur components associated with second and third order nonlinearities, as well as for the expected suppression achieved by the linearization technique depending on the number of SDMs used. In particular, the effect of the accompanying phase rotation introduced by time-offsetting the SDMs is investigated under two conditions: one in which the phase rotation is compensated, and another in which it is left uncompensated. The analysis shows that effective suppression of third order nonlinearities requires compensating for this phase rotation. However, the suppression of second order nonlinearities remains largely insensitive to phase alignment, demonstrating robustness of the technique to phase offsets in that case. In addition, the quantization-noise interaction between the different parallel SDM paths is examined and characterized through simulations. The results demonstrate that the technique significantly improves linearity while also suppressing quantization noise from the SDM. Finally, an efficient hardware implementation is proposed.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"21-32"},"PeriodicalIF":2.4,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11357518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0