IEEE open journal of circuits and systems最新文献

{"title":"End-to-End Neural Video Compression: A Review","authors":"Jiovana S. Gomes;Mateus Grellert;Fábio L. L. Ramos;Sergio Bampi","doi":"10.1109/OJCAS.2025.3559774","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3559774","url":null,"abstract":"The pervasive presence of video content has spurred the development of advanced technologies to manage, process, and deliver high-quality content efficiently. Video compression is crucial in providing high-quality video services under limited network and storage capacities, traditionally achieved through hybrid codecs. However, as these frameworks reach a performance bottleneck with compression gains becoming harder to achieve with conventional methods, Deep Neural Networks (DNNs) offer a promising alternative. By leveraging DNNs’ nonlinear representation capacity, these networks can enhance compression efficiency and visual quality. Neural Video Coding (NVC) has recently received significant attention, with Neural Image Coding models surpassing traditional codecs in compression ratios. Therefore, this survey explores the state-of-the-art in NVC, examining recent works, frameworks, and the potential of this innovative approach to revolutionize video compression. We identify that NVC models have come a long way since the first proposals and currently are on par in compression efficiency with the latest hybrid codec, VVC. Still, many improvements are required to enable the practical usage of NVC, such as hardware-friendly development to enable faster inference and execution on mobile and energy-constrained devices.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"120-134"},"PeriodicalIF":2.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10962175","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143848781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a High Efficiency Bi-Directional Four-Switch Buck-Boost Converter With HV Gate Driver for Multi-Cell Battery Power Bank Applications","authors":"Sung-June Byun;Byeong-Gi Jang;Jong-Wan Jo;Dae-Young Choi;Young-Gun Pu;Sang-Sun Yoo;Seok-Kee Kim;Yeon-Jae Jung;Kang-Yoon Lee","doi":"10.1109/OJCAS.2025.3557835","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3557835","url":null,"abstract":"This paper presents a bidirectional Four-Switch Buck-Boost (FSBB) converter with a high-voltage (HV) gate driver for use in power bank applications. The proposed FSBB is also integrated into this converter for increased efficiency. Thus, the proposed buck-boost converter can reduce conduction loss over a wide input voltage range by reducing the on-resistance of external MOSFETs using a gate source voltage (VGS) of 5V or 10V. The chip to be examined in this study is fabricated using a 130 nm 1P5M bipolar-CMOS-DMOS HV process with laterally diffused MOSFET (LDMOS) options to have a die size of 2.7 x 2.7 mm2. The proposed architecture is found to achieve a maximum output power level of 40W. The measurement results show that the maximum efficiencies at gate-source voltages (VGS) of 5V and 10V are 96.67% and 98.15%, respectively.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"110-119"},"PeriodicalIF":2.4,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10949157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications","authors":"Amirhossein Rostami;Seyed Mohammad Ali Zeinolabedin;Liyuan Guo;Florian Kelber;Heiner Bauer;Andreas Dixius;Stefan Scholze;Marc Berthel;Dennis Walter;Johannes Uhlig;Bernhard Vogginger;Christian Mayr","doi":"10.1109/OJCAS.2025.3546067","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3546067","url":null,"abstract":"Over the last few years, online training of deep neural networks (DNNs) on edge and mobile devices has attracted increasing interest in practical use cases due to their adaptability to new environments, personalization, and privacy preservation. Despite these advantages, online learning on resource-restricted devices is challenging. This work demonstrates a 16-bit floating-point, flexible, power- and memory-efficient neural learning unit (NLU) that can be integrated into processors to accelerate the learning process. To achieve this, we implemented three key strategies: a dynamic control unit, a tile allocation engine, and a neural compute pipeline, which together enhance data reuse and improve the flexibility of the NLU. The NLU was integrated into a system-on-chip (SoC) featuring a 32-bit RISC-V core and memory subsystems, fabricated using GlobalFoundries 22nm FDSOI technology. The design occupies just <inline-formula> <tex-math>$0.015mm^{2}$ </tex-math></inline-formula> of silicon area and consumes only 0.379 mW of power. The results show that the NLU can accelerate the training process by up to <inline-formula> <tex-math>$24.38times $ </tex-math></inline-formula> and reduce energy consumption by up to <inline-formula> <tex-math>$37.37times $ </tex-math></inline-formula> compared to a RISC-V implementation with a floating-point unit (FPU). Additionally, compared to the state-of-the-art RISC-V with vector coprocessor, the NLU achieves <inline-formula> <tex-math>$4.2times $ </tex-math></inline-formula> higher energy efficiency (measured in GFLOPS/W). These results demonstrate the feasibility of our design for edge and IoT devices, positioning it favorably among state-of-the-art on-chip learning solutions. Furthermore, we performed mixed-precision on-chip training from scratch for keyword spotting tasks using the Google Speech Commands (GSC) dataset. Training on just 40% of the dataset, the NLU achieved a training accuracy of 89.34% with stochastic rounding.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"85-99"},"PeriodicalIF":2.4,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10904478","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nonlinear Analysis of Differential LC Oscillators and Injection Locked Frequency Dividers","authors":"Konstantinos Metaxas;Vassilis Alimisis;Costas Oustoglou;Yannis Kominis;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2025.3545904","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3545904","url":null,"abstract":"A comprehensive nonlinear analysis of autonomous and periodically forced fully-differential, negative-resistor LC oscillators is presented. Through nonlinear transformations in the state space, it is shown that oscillators within this class exhibit qualitatively similar dynamical behavior in terms of their limit cycles and bifurcation curves, at least within an open region containing the origin. The case of autonomous, complementary BJT oscillators is used to validate the qualitative analysis and demonstrate a general approach of how to numerically extend the bifurcation curves away from the equilibrium point and determine the oscillatory conditions. When external periodic force is present, we focus on the special case of periodically multiplicatively-forced fully-differential, negative-resistor, LC oscillators and use Harmonic Balance techniques to derive analytical expressions estimating the locking range in the weak injection regime. The results are used to calculate the locking range of a harmonically forced complementary BJT oscillator yielding explicit expressions closely aligned with experimental measurements, thus verifying the validity of the analysis.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"100-109"},"PeriodicalIF":2.4,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10904493","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy Consumption Modeling of 2-D and 3-D Decoder Circuits","authors":"Yufei Xiao;Kai Cai;Xiaohu Ge;Yong Xiao","doi":"10.1109/OJCAS.2025.3538707","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3538707","url":null,"abstract":"Energy consumption evaluation for data processing tasks, such as encoding and decoding, is a critical consideration in designing very large scale integration (VLSI) circuits. Incorporating both information theory and circuit perspectives, a new general energy consumption model is proposed to capture the energy consumption of channel decoder circuits. For the binary erasure channel, lower bounds of energy consumption are derived for two-dimensional (2D) and three-dimensional (3D) decoder circuits under specified error probabilities, along with scaling rules for energy consumption in each case. Based on the proposed model, the lower bounds of energy consumption for staged serial and parallel implementations are derived, and a specific threshold value is identified to determine the parallel or serial decoding in decoder circuits. Staged serial implementations in 3D decoder circuits achieve a higher energy efficiency than fully parallel implementations when the processed data exceed 48 bits. Simulation results further demonstrate that the energy efficiency of 3D decoders improves with increasing data volume. When the number of input bits is 648, 1296 and 1944, the energy consumption of 3D decoders is reduced by 11.58%, 13.07%, and 13.86% compared to 2D decoders, respectively. The energy consumption of 3D decoders surpasses that of 2D decoders when the decoding error probability falls below a specific threshold of 0.035492. These results provide a foundational framework and benchmarks for analyzing and optimizing the energy consumption of 2D and 3D channel decoder circuits, enabling more efficient VLSI circuit designs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"74-84"},"PeriodicalIF":2.4,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10870295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2024 Index IEEE Open Journal of Circuits and Systems Vol. 5","authors":"","doi":"10.1109/OJCAS.2025.3533978","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3533978","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"408-417"},"PeriodicalIF":2.4,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854515","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society","authors":"","doi":"10.1109/OJCAS.2025.3525785","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3525785","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10834607","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Verilog-A Modeling of Floating-Gate Transistors","authors":"Sayma Nowshin Chowdhury;Matthew Chen;Sahil Shah","doi":"10.1109/OJCAS.2024.3524363","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3524363","url":null,"abstract":"Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"63-73"},"PeriodicalIF":2.4,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818976","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society","authors":"","doi":"10.1109/OJCAS.2024.3517215","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3517215","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10805493","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Instruction for Authors","authors":"","doi":"10.1109/OJCAS.2024.3517219","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3517219","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"408-408"},"PeriodicalIF":2.4,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10805492","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142843066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}