IEEE open journal of circuits and systems最新文献

{"title":"A Review on Sub-0.21-V Ultra-Low-Supply-Voltage Analog-to-Digital Converters","authors":"Eric Christie;Jared Marchant;Shea Smith;Long Kong;Chia-Hung Chen;Shiuh-Hua Wood Chiang","doi":"10.1109/OJCAS.2025.3574336","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3574336","url":null,"abstract":"Ultra-low-supply-voltage (ULV) analog-to-digital converters (ADCs) operating at 0.21 V or lower are attractive for Internet-of-Things (IoT) and embedded applications due to their extremely low power consumption. This paper surveys state-of-the-art ULV ADCs to evaluate current trends and design strategies. Architectures, circuit implementations, and calibration techniques are analyzed and key trends are identified. Based on the observations, the paper provides recommendations for the circuit designer to make judicious design choices to obtain the desired performance for ULV ADCs. This paper further explores the VCO-based architecture and proposes a new topology to achieve high resolution for ULV ADCs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"228-240"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106915","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC","authors":"Wenhao Wu;Fei Yuan;Yushi Zhou","doi":"10.1109/OJCAS.2025.3586748","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3586748","url":null,"abstract":"This paper presents a sub-threshold all-digital delay-locked loop (DLL) for the generation of the timing signals of low-power low-data-rate successive approximation register analog-to-digital converters. The delay line of the DLL consists of a set of cascaded static inverters with its large per-stage-delay obtained by powering the delay with an exceedingly low supply voltage. The per-stage-delay of the delay line is adjusted by varying the supply voltage provided by a sub-threshold voltage generator. Voltage recovery blocks consisting of cascaded static inverters with different supply voltages are used to recover the low voltage swing of the delay line to the nominal voltage swing of the DLL. High-voltage-threshold pMOS transistors are used to minimize the short-circuit-induced power consumption of voltage-recovering inverters. The proposed DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3v3 device models. Simulation results show the DLL locks to a <inline-formula> <tex-math>$0sim 0.6$ </tex-math></inline-formula> V 100 kHz 50% duty cycle external timing reference at FF/0.6V/-<inline-formula> <tex-math>$20^{o}$ </tex-math></inline-formula>C, TT/0.6V/<inline-formula> <tex-math>$27^{o}$ </tex-math></inline-formula>C, and SS/0.6V/<inline-formula> <tex-math>$60^{o}$ </tex-math></inline-formula>C in approximately 7 cycles of the timing reference with no accumulated static phase errors. The DLL occupies an area of 0.00559 mm2, offers 0.35% normalized root-mean-square jitter, and consumes 92 nW.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"270-282"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106517","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison and Design of Linear and Exponential Integrated Charge Pumps","authors":"Masoud Askariraad;Stefano Gregori","doi":"10.1109/OJCAS.2025.3583268","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3583268","url":null,"abstract":"This paper presents static and dynamic models for linear and exponential integrated charge pumps in both step-up and step-down modes. The static models are used to compare the slow-switching and fast-switching output resistance of various configurations, considering optimized and non-optimized capacitors and switches. In the dynamic models, the self-loading capacitance is determined using a simpler approach than previous works, allowing for a more straightforward comparison of the start-up time and charging efficiency. To highlight the differences between linear and exponential charge pumps, the working voltages of capacitors and switches are calculated, with these expressions guiding the selection of the most appropriate devices for each configuration. Additionally, parasitic capacitances and leakage currents are modeled and analyzed across the circuit configurations, and their impact on overall efficiency is assessed. The procedure for optimally sizing capacitors and switches using different device types is then discussed. Finally, two design examples in 65-nm CMOS technology are presented to validate the models, demonstrate design procedures, and highlight the advantages and limitations of practical implementations of each circuit.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"295-312"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106932","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC","authors":"Fei Yuan","doi":"10.1109/OJCAS.2025.3565921","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3565921","url":null,"abstract":"This paper provides a critical review and the classification of comparators in low-power low-data-rate (1 kS/s~1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs). Both voltage-domain and time-domain comparators are studied and their pros and cons are examined. The architecture, comparison time, and power consumption of five widely used voltage-domain dynamic comparators are studied first. It is followed with an investigation of kickback in comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converters (DACs) of SAR ADCs arising from the different resistances of DAC switches gives rise to a differential clock kickback that occurs earlier than output kickback with more strength hence dictating kickback in dynamic comparators. If the strength and duration of clock kickback are sufficiently large, the comparator will yield an erroneous output. The dependence of clock kickback on the input of SAR ADCs in the least significant bit (LSB) conversion is also investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are investigated, and the minimum tuning bits of digitally tuned offset compensation capacitor arrays is obtained. The noise of dynamic comparators is also investigated and design trade-offs between noise, power consumption, kickback, and the loading of the comparator on DAC are examined. The extensive simulation results of the comparators designed in a TSMC 130 nm 1.2 V CMOS technologies with reduced supply voltages and analyzed using Spectre from Cadence Design Systems with BSIM 3.3 device models are provided.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"241-256"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Systematic Design of Ring VCO-Based SNN—Translating Training Parameters to Circuits","authors":"Sai Sanjeet;Sanchari Das;Shiuh-Hua Wood Chiang;Masahiro Fujita;Bibhu Datta Datta","doi":"10.1109/OJCAS.2025.3585654","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3585654","url":null,"abstract":"The deployment of digitally-trained analog Spiking Neural Networks (SNNs) presents a promising approach for energy-efficient edge computing. However, training such networks is not trivial, and discrepancies between digital training models and their continuous-time analog implementations pose challenges in validation and performance verification. This paper aims to bridge the gap between the design of analog neuron models and training SNNs with the neuron model, along with a time-domain verification framework that enables circuit designers to validate their analog SNN implementations in a simulation environment resembling industry-standard EDA tools such as Cadence and Synopsys while offering significantly faster execution. This work focuses on a ring oscillator-based neuron model, which realizes the leaky integrate-and-fire (LIF) neuron. The design of the ring oscillator-based neuron is discussed, and the neuron model is digitized using the bilinear transform to enable training. The trained network is used to classify the MNIST dataset with an accuracy of 97.35% and the Iris dataset with an accuracy of 93.33%. We further introduce a time-domain verification framework based on Simulink to validate the trained networks. We verify our approach by comparing digitally-trained PyTorch models against analog implementations simulated using our framework on the Iris dataset, revealing accuracy discrepancies between the analog and digital counterparts, along with insights into the cause of such discrepancies, which would have been difficult to simulate with SPICE simulators. Additionally, we verify the generated Simulink models against Verilog-A models simulated in Cadence Spectre, demonstrating that our framework produces identical outputs while achieving an order-of-magnitude speedup. By providing an efficient, accurate, and accessible verification platform, our framework bridges the gap between digital training and analog hardware verification, facilitating the development of robust, high-performance SNNs for edge applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"283-294"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106930","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Biologically-Inspired, Ultra-Low Power, and High-Speed Integrate-and-Fire Neuron Circuit With Stochastic Behavior Using Nanoscale Side-Contacted Field Effect Diode Technology","authors":"Seyedmohamadjavad Motaman;Sarah S. Sharif;Yaser M. Banad","doi":"10.1109/OJCAS.2025.3549442","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3549442","url":null,"abstract":"Enhancing power efficiency and performance in neuromorphic computing systems is critical for next-generation artificial intelligence applications. We propose the Nanoscale Side-contacted Field Effect Diode (S-FED)—a novel solution that significantly lowers power usage and improves circuit speed—enabling efficient neuron circuit design. Our proposed integrate-and-fire (IF) neuron model demonstrates remarkable performance metrics: 44 nW power consumption (85% lower than current designs), 0.964 fJ energy per spike (36% improvement over state-of-the-art), and a spiking frequency ranging from 20 to 100 MHz. Moreover, we show how to bias the circuit to enable both deterministic and stochastic operation, mimicking key computational features of biological neurons. The stochastic behavior can be precisely controlled through reference voltage modulation, achieving firing probabilities from 0% to 100% and enabling probabilistic computing capabilities. The architecture exhibits robust stability across process (channel length and doping)-voltage-temperature (PVT) variations, maintaining consistent performance with less than 7% spike amplitude variation for channel lengths from 7.5nm to 15nm, doping from <inline-formula> <tex-math>$5times 10{^{{20}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^ - 3 $ </tex-math></inline-formula> to <inline-formula> <tex-math>$1times 10{^{{2}}} {^{{1}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^ - 3 $ </tex-math></inline-formula>, supply voltages from 0.8V to 1.2V, and temperatures spanning −40°C to 120°C. The model features tunable thresholds (0.8V to 1.4V) and reliable operation across input spike pulse widths from 0.5 ns to 2 ns. This advancement in neuromorphic hardware paves the way for more efficient brain-inspired computing systems.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"217-227"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106515","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Lightweight Hybrid Random Number Generator With Dynamic Entropy Injection","authors":"Sonia Akter;Shelby Williams;Prosen Kirtonia;Magdy Bayoumi;Kasem Khalil","doi":"10.1109/OJCAS.2025.3582975","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3582975","url":null,"abstract":"This paper presents a lightweight hybrid random number generator (HRNG), implemented and evaluated on a Field-Programmable Gate Array (FPGA). The proposed design enhances security and randomness by synergizing jitter and metastability using a feedforward topology, which achieves a near-perfect Shannon entropy. Moreover, it is validated using three distinct entropy metrics, guaranteeing statistically robust random numbers for security-sensitive applications. In addition to entropy evaluations, this design is also rigorously analyzed using multiple industry-standard randomness test suites. Beyond the FPGA implementation, this work presents performance metrics, including area utilization, power consumption, maximum frequency, and energy usage per random bit, which are synthesized across three different technology nodes in Synopsys Design Compiler (SDC). All of the results from the FPGA and the SDC implementations demonstrate significant improvements. These results confirm the design’s scalability to advance technology nodes and its suitability for applications that require secure and reliable random number generation, such as resource-efficient Internet of Things (IoT) devices.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"257-269"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106931","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"L-Sort: On-Chip Spike Sorting With Efficient Median-of-Median Detection and Localization-Based Clustering","authors":"Yuntao Han;Yihan Pan;Xiongfei Jiang;Cristian Sestito;Shady Agwa;Themis Prodromakis;Shiwei Wang","doi":"10.1109/OJCAS.2025.3584317","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3584317","url":null,"abstract":"Spike sorting is a critical process for decoding large-scale neural activity from extracellular recordings. The advancement of neural probes facilitates the recording of a high number of neurons with an increase in channel counts, arising a higher data volume and challenging the current on-chip spike sorters. This paper introduces L-Sort, a novel on-chip spike sorting solution featuring median-of-median spike detection and localization-based clustering. By combining the median-of-median approximation and the proposed incremental median calculation scheme, our detection module achieves a reduction in memory consumption. Moreover, the localization-based clustering utilizes geometric features instead of morphological features, thus eliminating the memory-consuming buffer for containing the spike waveform during feature extraction. Evaluation using Neuropixels datasets demonstrates that L-Sort achieves competitive sorting accuracy with reduced hardware resource consumption. Implementations on FPGA and ASIC (180 nm technology) demonstrate significant improvements in area and power efficiency compared to state-of-the-art designs while maintaining comparable accuracy. If normalized to 22 nm technology, our design can achieve roughly <inline-formula> <tex-math>$times 10$ </tex-math></inline-formula> area and power efficiency with similar accuracy, compared with the state-of-the-art design evaluated with the same dataset. Therefore, L-Sort is a promising solution for real-time, high-channel-count neural processing in implantable devices.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"205-216"},"PeriodicalIF":2.4,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11072521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BAG3++: An Extensible Generator Framework for Automated Layout-Aware AMS Design","authors":"Felicia Guo;Bob Zhou;Ayan Biswas;Paul Kwon;Zhaokai Liu;Ken Ho;Vladimir Stojanović;Borivoje Nikolić","doi":"10.1109/OJCAS.2024.3502641","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3502641","url":null,"abstract":"We present BAG<inline-formula> <tex-math>$3{++}$ </tex-math></inline-formula>, an extensible analog/mixed-signal (AMS) design framework for layout-aware design. BAG<inline-formula> <tex-math>$3{++}$ </tex-math></inline-formula> realizes a unified design environment that merges schematic, layout, and verification views into a single development interface. We further introduce new automated design features that enable rapid automation and optimization across a range of performance specifications, processes, and applications. We demonstrate the practical use of these features through (a) a bit-reconfigurable successive-approximation-register (SAR) analog-to-digital converter (ADC) implemented in the open-source Skywater 130nm process and (b) an ultra-high speed output driver optimized in two modern processes. BAG<inline-formula> <tex-math>$3{++}$ </tex-math></inline-formula> interfaces with both commercial and open-source design frameworks, and the extensibility of BAG<inline-formula> <tex-math>$3{++}$ </tex-math></inline-formula> is further illustrated through the integration of an open-source simulator.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"181-191"},"PeriodicalIF":2.4,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11052889","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Revolutionize 3D-Chip Design With Open3DFlow, an Open-Source AI-Enhanced Solution","authors":"Yifei Zhu;Zhenxuan Luan;Dawei Feng;Weiwei Chen;Lei Ren;Zhangxi Tan","doi":"10.1109/OJCAS.2024.3518754","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3518754","url":null,"abstract":"The escalating demand for high-performance and energy-efficient electronics has propelled 3D integrated circuits (3D ICs) as a promising solution. However, major obstacles have been the lack of specialized electronic design automation (EDA) software and standardized design flows for 3D chiplets. To bridge the gap, we introduce Open3DFlow,<xref>1</xref> an open-source design platform for 3D ICs. It is a seven-step workflow that incorporates essential ASIC back-end processes while supporting multi-physics analysis, such as through silicon via (TSV) modeling, thermal analysis, and signal integrity (SI) evaluations. To illustrate all functionalities of <italic>Open3DFlow</i>, we use it to implement a 3D RISC-V CPU design with a vertically stacked L2 cache on a separated die. We harden both CPU logic and 3D-cache die in a GlobalFoundries <inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>m (GF180) process with open-source PDK support. We enable face-to-face (F2F) coupling of the top and bottom die by constructing a bonding layer based on the original technology file. <italic>Open3DFlow</i>’s open-source nature allows seamless integration of custom AI optimization algorithms. As a showcase, we leverage large language models (LLMs) to help the bonding pad placement. In addition, we apply LLM on back-end Tcl script generations to improve design productivity. We expect <italic>Open3DFlow</i> to open up a brand-new paradigm for future 3D IC innovations.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"169-180"},"PeriodicalIF":2.4,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11052893","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}