IEEE open journal of circuits and systems最新文献_第2页

A GHz-Range Single-Bit Bandpass Delta-Sigma Modulator With FIR-DACs Achieving 64-dB SNDR Over 20-MHz Bandwidth 带fir - dac的ghz范围单比特带通Delta-Sigma调制器在20mhz带宽上实现64db SNDR

IF 1.8

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-03-14 DOI: 10.1109/OJCAS.2026.3693591

Javad Gorji;Luis A. Camuñas-Mesa;Shanthi Pavan;José M. De La Rosa

{"title":"A GHz-Range Single-Bit Bandpass Delta-Sigma Modulator With FIR-DACs Achieving 64-dB SNDR Over 20-MHz Bandwidth","authors":"Javad Gorji;Luis A. Camuñas-Mesa;Shanthi Pavan;José M. De La Rosa","doi":"10.1109/OJCAS.2026.3693591","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3693591","url":null,"abstract":"This paper presents the first circuit-level implementation of a continuous-time bandpass delta-sigma (<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>) modulator featuring a bandpass finite impulse response (BP-FIR) DAC in the feedback path. Targeting RF-sampling receiver architectures for reconfigurable multi-band front-ends, the fourth-order modulator employs an LC-based loop filter operating at a 4 GHz sampling frequency with a 1 GHz center frequency. By combining a single-bit quantizer with a BP-FIR feedback DAC, the architecture effectively suppresses out-of-band quantization noise and minimizes the voltage swing at the loop-filter input. This configuration directly addresses the key practical challenges of single-bit continuous-time <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> modulators by significantly relaxing the loop filter’s linearity requirements and mitigating clock jitter sensitivity, all while avoiding the stringent element-matching bottlenecks of multi-bit designs. Validated through layout-aware transistor-level simulations in 28 nm FD-SOI CMOS, the proposed design achieves an SFDR of 71.5 dB and an SNDR of 63.9 dB over a 20 MHz bandwidth while consuming 23.4 mW from a 1 V supply. Delivering a favorable trade-off between dynamic range, power consumption, and implementation complexity, the proposed design is well suited for integration into next-generation software-defined radio (SDR) systems.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"341-352"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11520339","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Multi-Point Sensitivity Approach for Stability Analysis of Multi-Loop LDOs 多环LDOs稳定性分析的多点灵敏度方法

IF 1.8

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-08-28 DOI: 10.1109/OJCAS.2026.3728204

Peijuan Ju;Qisong Wu;Dixian Zhao

引用次数: 0

RRNS Arith Lib—Open-Source Redundant Residue Number System Arithmetics for Reliable Circuits 可靠电路的冗余数系统算法

IF 1.8

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-07-27 DOI: 10.1109/OJCAS.2026.3717375

Tim Oberschulte;Enno Sievers;Holger Blume

{"title":"RRNS Arith Lib—Open-Source Redundant Residue Number System Arithmetics for Reliable Circuits","authors":"Tim Oberschulte;Enno Sievers;Holger Blume","doi":"10.1109/OJCAS.2026.3717375","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3717375","url":null,"abstract":"A Residue Number System (RNS) represents integers through a set of residues obtained by integer division using a predefined set of pairwise coprime moduli. RNS is well-known for enabling efficient carry-free arithmetic and representing large numbers with multiple shorter numerical values. By incorporating additional moduli, the system can be extended into an overdetermined Redundant Residue Number System (RRNS), introducing redundancy that facilitates the detection of bit errors. In this paper, we present the development of an open-source VHDL library designed for the integration of RRNS arithmetic into ASIC or FPGA architectures. The paper details the design considerations and evaluates the performance of the RRNS library on an FPGA, comparing it to conventional redundant binary arithmetic implementations. For an exemplary matrix multiplication, it is shown that RRNS is smaller and faster for numbers of more than 42 bit dynamic range. Furthermore, we demonstrate the error detection capabilities of the RRNS through a realistic real-world FPGA application, wherein faults are injected into the configuration memory to validate the system’s robustness. The results show better-than-DMR error detection performance of 99.9 % at the cost of an area overhead of about 18 %. In pre-layout ASIC designs, RRNS shows smaller area and power consumption (up to −60 %) than binary DMR while maintaining the same clock frequency.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"434-446"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11626132","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Machine-Learning Variation-Aware Co-Design for Analog Linearization of VCO-ADCs vco - adc模拟线性化的机器学习变化感知协同设计

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-04-27 DOI: 10.1109/OJCAS.2026.3676608

Viet Nguyen;Peter Kilgannon;Ciara Lambkin;Hieu Minh Nguyen;Robert Bogdan Staszewski

{"title":"Machine-Learning Variation-Aware Co-Design for Analog Linearization of VCO-ADCs","authors":"Viet Nguyen;Peter Kilgannon;Ciara Lambkin;Hieu Minh Nguyen;Robert Bogdan Staszewski","doi":"10.1109/OJCAS.2026.3676608","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3676608","url":null,"abstract":"This article introduces a machine-learning (ML)-driven co-design and optimization framework for open-loop analog linearization of VCO-ADCs, especially operating in the low supply-voltage (VDD) regime, and demonstrated on a new coupled-oscillator-ensemble (COE) circuit architecture. The high-dimensional optimization space associated with the embedded linearization tuning ‘knobs’ of the VCOs renders exhaustive transistor-level search infeasible. To address this challenge, a deep neural network (DNN) surrogate is trained on a compact set of transistor-level transient simulations capturing the COE’s composite voltage-to-frequency (<inline-formula> <tex-math>$V$ </tex-math></inline-formula>-to-<inline-formula> <tex-math>$f$ </tex-math></inline-formula>) characteristics. This surrogate enables rapid exploration of the vast tuning-knob landscape and steers an evolutionary genetic algorithm (GA) toward configurations that optimize harmonic distortion (HD). To further enhance HD-prediction robustness and incorporate VDD variation awareness, the framework integrates advanced ML techniques. Monte Carlo (MC)–perturbed GA optimization improves resilience to parameter uncertainty, while a stacked-ensemble surrogate network, constructed from expert-VDD-specific base models fused with a hybrid encoder-combiner meta-learner, facilitates accurate VDD–aware predictions. The resulting optimized tuning settings are transferred to a Cadence simulation environment for transistor-level verification of the VCO–ADC, achieving a mean third-order harmonic distortion (<inline-formula> <tex-math>$text {HD}_{3}$ </tex-math></inline-formula>) of 55 dB. Across a wide 0.4—0.6 V supply range (<inline-formula> <tex-math>$approx 40%$ </tex-math></inline-formula> variation), <inline-formula> <tex-math>$text {HD}_{3}$ </tex-math></inline-formula> remains above 50 dB through the DNN’s supply-adaptive dynamic programming of the tuning-knob values.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"193-205"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11495329","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 73-dB PSR Trimless CMOS-Only Subthreshold Current-Mode Voltage Reference for Harsh-Environment Operation Using CTAT Current Subtraction 基于CTAT电流减法的73 db PSR无Trimless cmos亚阈值电流模式电压基准

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-06-02 DOI: 10.1109/OJCAS.2026.3698779

Reza Papi;Benoit Gosselin

{"title":"A 73-dB PSR Trimless CMOS-Only Subthreshold Current-Mode Voltage Reference for Harsh-Environment Operation Using CTAT Current Subtraction","authors":"Reza Papi;Benoit Gosselin","doi":"10.1109/OJCAS.2026.3698779","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3698779","url":null,"abstract":"A new CMOS-only voltage reference, operating in current mode and leveraging subthreshold MOSFETs, is presented in this paper. In contrast to conventional solutions that sum PTAT and CTAT currents to provide a constant voltage reference, the proposed design introduces a zero temperature coefficient current by subtracting two CTAT currents—representing a key design novelty. Moreover, the presented approach does not use any trimming scheme to generate the output voltage.By eliminating bulky Bipolar Junction Transistors (BJTs), the circuit significantly reduces both area and power consumption while retaining robust performance in harsh environments over a temperature range from −20°C to 150°C. Fabricated in TSMC 130-nm CMOS technology, it delivers an output voltage near 610 mV with a measured temperature coefficient (TC) ranging from 188 ppm/°C to 212 ppm/°C across different chips. Owing to its current-mode operation, the voltage reference level can be readily adjusted through the decoder’s inputs, providing flexibility for a variety of applications. Measurement results confirm a power supply rejection (PSR) of −73 dB and a quiescent current of 3.2 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A from a 1.2 V supply, making this trimless voltage reference an attractive option for compact, low-power systems.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"330-340"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11547173","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA-Based Softmax Approximation: Analytical Cost–Error Modeling and Pareto Optimization 基于fpga的Softmax逼近：分析成本误差建模和Pareto优化

IF 1.8

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-09-14 DOI: 10.1109/OJCAS.2026.3731578

Mouna Djellouli;Amirhossein Zarei;Atik Mahabub;Hamza Bendaoudi;Shervin Vakili

{"title":"FPGA-Based Softmax Approximation: Analytical Cost–Error Modeling and Pareto Optimization","authors":"Mouna Djellouli;Amirhossein Zarei;Atik Mahabub;Hamza Bendaoudi;Shervin Vakili","doi":"10.1109/OJCAS.2026.3731578","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3731578","url":null,"abstract":"The softmax function is a significant bottleneck in FPGA-based Transformer inference. This paper presents a comprehensive analytical framework for the design and optimization of base-2 softmax on FPGAs through systematic design-space exploration. We derive a high-accuracy LUT6 cost model that captures all major pipeline components, along with a closed-form error model for the exponential approximation, validated against Monte Carlo simulation with deviations below 10% for MSE and within 2% for MAE. By jointly leveraging these models, we exhaustively explore the design space and identify Pareto-optimal configurations that minimize LUT6 usage for a given relative error target. We further propose a negligible-cost fixed-maximum-subtraction scheme that eliminates the sorting network required by prior work, and introduce a bipartite exponential architecture that removes the intrinsic approximation floor of piecewise-linear methods. Synthesis and implementation on a Xilinx UltraScale+ FPGA confirm the effectiveness of the proposed approach. For a single-lane configuration, the optimized core requires only 201 LUT6s to achieve a relative MSE below <inline-formula> <tex-math>$10^{-10}$ </tex-math></inline-formula>, corresponding to an approximately 49% reduction in resource utilization compared to the closest prior work at comparable accuracy.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"519-530"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11690901","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149131843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

8-Channel CMOS Chip for Real-Time Control of Integrated Silicon Photonic Processors 集成硅光子处理器实时控制的8通道CMOS芯片

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2025-12-19 DOI: 10.1109/OJCAS.2025.3609034

Emanuele Sacchi;Francesco Zanetto;Andres Ivan Martinez;SeyedMohammad SeyedinNavadeh;Francesco Morichetti;Andrea Melloni;Marco Sampietro;Giorgio Ferrari

{"title":"8-Channel CMOS Chip for Real-Time Control of Integrated Silicon Photonic Processors","authors":"Emanuele Sacchi;Francesco Zanetto;Andres Ivan Martinez;SeyedMohammad SeyedinNavadeh;Francesco Morichetti;Andrea Melloni;Marco Sampietro;Giorgio Ferrari","doi":"10.1109/OJCAS.2025.3609034","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3609034","url":null,"abstract":"Photonic integrated circuits (PICs) allow to implement linear operations directly in the light domain, taking advantage of the extended bandwidth, low losses and minimal cross-talk associated with optical communication. These architectures benefit from the addition of dedicated electronics that enable run-time programmability, as well as closed-loop stabilization of the working point against drifts and turbulence. This work addresses the issue of the scalability, in terms of area and power consumption, of the electronic control layer, by proposing an application-specific integrated circuit (ASIC) designed for real-time reconfiguration of programmable optical processors. The CMOS controller features 8 independent channels, each one closing a feedback control loop around an integrated photonic interferometric device. In the experiments, a pair of ASICs was connected to a 16-channel binary mesh consisting of 15 Mach-Zehnder Interferometers fabricated in a commercial Silicon Photonics platform. The resulting electronic-photonic chiplet-like system successfully established reliable free-space optical (FSO) links up to 50 Gbit/s, compensating the effect of simulated atmospheric turbulence. The inherent ability of the ASIC to drive each photonic device independently, though, makes it suitable also for applications beyond sheer working point stabilization, whenever a full reconfiguration of the PIC is needed, achieving sub-10 ms settling time when starting from a random working point. The proposed integrated design thus paves the way for the definition of compact and seamlessly scalable electronic controllers for programmable PICs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"206-217"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304253","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Quadrature-Phase Sampling Technique for Filterless, Low-Complexity, High-Alias-Suppression in VCO-ADCs 一种新的无滤波器、低复杂度、高混叠抑制的正交相位采样技术

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-04-29 DOI: 10.1109/OJCAS.2025.3631878

Jinhen Lee;Victor Adrian;Joseph S. Chang

{"title":"A Novel Quadrature-Phase Sampling Technique for Filterless, Low-Complexity, High-Alias-Suppression in VCO-ADCs","authors":"Jinhen Lee;Victor Adrian;Joseph S. Chang","doi":"10.1109/OJCAS.2025.3631878","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3631878","url":null,"abstract":"Next-generation LiDAR systems demand unprecedented resolution, requiring wide signal bandwidth and high-density pixel arrays that constrain each pixel circuit to <inline-formula> <tex-math>$leq 0.01$ </tex-math></inline-formula> mm2. This limits the complexity and power available for anti-aliasing filtering in the receiver front-end, even though strong attenuation of interference and alias noise is critical to preserve signal fidelity. Voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs) offer inherent anti-aliasing through spectral shaping, but for bandwidths <inline-formula> <tex-math>$geq $ </tex-math></inline-formula>50 MHz, the attenuation is insufficient, necessitating dedicated analog filters that undermine area and power. To resolve this, we propose a novel sampling technique for VCO-ADCs, employing quadrature clocks instead of conventional clocking. The resulting output spectrum exhibits a quasi-<inline-formula> <tex-math>$sinc^{3}$ </tex-math></inline-formula>-shaped response that improves alias attenuation by ~10 dB to 80 dB at 50 MHz bandwidth—the highest reported to date—eliminating the need for analog filters. We derive an analytical expression for this response, accounting for non-idealities and offering insight into the parameters governing the shaping behavior. The technique is demonstrated with a proposed filterless, low-complexity VCO-ADC circuit in CMOS 65 nm, occupying just 0.0017 mm2—43% smaller than the state-of-the-art—and dissipating only 0.42 mW at 2 GHz sampling in simulation. Benchmarking shows a figure-of-merit of 56 fJ/conversion-step, <inline-formula> <tex-math>$sim 1.1times $ </tex-math></inline-formula> better than the best reported design.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"218-229"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11500574","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Voltage-Dependent Resistance Ratio in HfO2-Based Resistive RAM on Non-Stateful Logic 基于hfo2的电阻式RAM中电压相关电阻比对无状态逻辑的影响

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2025-12-18 DOI: 10.1109/OJCAS.2025.3617796

Thomas Neuner;Shahar Kvatinsky

{"title":"Impact of Voltage-Dependent Resistance Ratio in HfO2-Based Resistive RAM on Non-Stateful Logic","authors":"Thomas Neuner;Shahar Kvatinsky","doi":"10.1109/OJCAS.2025.3617796","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3617796","url":null,"abstract":"Emerging nonvolatile memory technologies offer promising avenues for novel computing approaches. Among them, resistive random access memories (RRAMs) stand out due to their nonvolatility, fast switching speed, compact size, and low power consumption. Logic techniques such as complementary resistive switch (CRS) and memristor ratioed logic (MRL) are prominent non-stateful logic techniques. CRS is well-suited for crossbar arrays, mitigating sneak-path currents, while MRL integrates effectively with CMOS logic, enabling the construction of complete logic circuits using CMOS inverters. Both techniques share a common trait: their logical output is read/defined under a high input voltage. However, the nonlinear I-V characteristics of RRAM devices reduce the resistance ratio, limiting reliable logic operation. This paper experimentally demonstrates CRS and MRL gates using HfO2 memristors within a crossbar array. We show that the voltage-dependent resistance degradation of the high-resistance state (HRS) significantly reduces the resistance ratio during logic evaluation, impairing output reliability and cascading potential. Simulation results confirm these nonlinear effects. To address these challenges, we introduce a two-phase read scheme for CRS and a pre-initialization strategy for MRL that sets both devices to HRS before operation. These methods improve current spike detectability and enhance output voltage levels, respectively. The proposed solutions advance the feasibility of robust in-memory logic with nonlinear memristive devices.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"184-192"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304252","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Piecewise Linear Model of Loss Estimation for Switched-Inductor Power Management Integrated Circuits 开关电感电源管理集成电路损耗估计的分段线性模型

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-03-18 DOI: 10.1109/OJCAS.2026.3694454

Yi-Fu Chen;Bo-Ray Chen;Yun-Yin Kuo;Philex Ming-Yan Fan

{"title":"A Piecewise Linear Model of Loss Estimation for Switched-Inductor Power Management Integrated Circuits","authors":"Yi-Fu Chen;Bo-Ray Chen;Yun-Yin Kuo;Philex Ming-Yan Fan","doi":"10.1109/OJCAS.2026.3694454","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3694454","url":null,"abstract":"This paper proposes a piecewise linear mathematical model for estimating power losses and power conversion efficiency in switched-inductor power management integrated circuits. By exploiting the parasitic resistance extracted from metal routing wires, vias, pads, and bonding wires as well as devices’ on-resistance in the power delivery path, this model provides a time-efficient method useful for the pre-layout design stage. The proposed approach significantly reduces the iteration of circuit design and layout required to achieve optimal power efficiency in PMICs. Additionally, it can accurately predict power loss breakdown in just a few minutes, compared to several weeks or even more spent on post-layout simulation. The results of the proposed model demonstrate a good agreement with that of the simulation program with integrated circuit emphasis (SPICE) simulations and silicon measurements. The silicon prototype is implemented in a <inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>m CMOS technology and achieves peak power conversion efficiencies of 95.3% for single-inductor single-output operation and 92% for single-inductor four-output operation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"319-329"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11523507","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0