IEEE open journal of circuits and systems最新文献_第2页

V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation V2Va +：用于加速混合信号仿真的高效 SystemVerilog 和 Verilog-to-Verilog-A 转换器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-16 DOI: 10.1109/OJCAS.2024.3451530

Chao Wang;Yicong Shao;Jiajie Huang;Wangzilu Lu;Zhiwen Gu;Longfan Li;Yuhang Zhang;Jian Zhao;Wei Mao;Yongfu Li

{"title":"V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation","authors":"Chao Wang;Yicong Shao;Jiajie Huang;Wangzilu Lu;Zhiwen Gu;Longfan Li;Yuhang Zhang;Jian Zhao;Wei Mao;Yongfu Li","doi":"10.1109/OJCAS.2024.3451530","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3451530","url":null,"abstract":"This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over \u0000<inline-formula> <tex-math>$2{times }$ </tex-math></inline-formula>\u0000. These strengths underscore its significant impact and applicability in the domain of circuit design.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"387-397"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability 一种具有类cpu可编程性的高能效顺序可重构阵列

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-16 DOI: 10.1109/OJCAS.2024.3518110

Tobias Kaiser;Esther Gottschalk;Kai Biethahn;Friedel Gerfers

{"title":"Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability","authors":"Tobias Kaiser;Esther Gottschalk;Kai Biethahn;Friedel Gerfers","doi":"10.1109/OJCAS.2024.3518110","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3518110","url":null,"abstract":"This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"1-13"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10802954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model 亚太赫兹信道模型下多流MIMO系统的同步与信道估计设计

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-04 DOI: 10.1109/OJCAS.2024.3510921

Chung-Lun Tu;Chen-Yuan Tseng;Wei-Che Lee;Kang-Lun Chiu;Pei-Yun Tsai;Shyh-Jye Jou

{"title":"Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model","authors":"Chung-Lun Tu;Chen-Yuan Tseng;Wei-Che Lee;Kang-Lun Chiu;Pei-Yun Tsai;Shyh-Jye Jou","doi":"10.1109/OJCAS.2024.3510921","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3510921","url":null,"abstract":"This article presents an advanced synchronization and channel estimation architecture for multi-stream MIMO systems in sub-terahertz environments. To streamline hardware complexity, we employ Golay cross-correlation across all detection and estimation schemes. Key innovations include a precise timing detection algorithm that utilizes pulse shaping impulse response and quadratic regression, along with multiple window-based approaches to enhance performance against non-ideal effects. At the architectural level, a shared optimized Golay correlator reduces hardware usage by 23%, efficiently handling multiple correlation lengths in a single design. Additionally, we propose an indexing-count method that addresses sorting challenges, achieving notable improvements in processing speed and complexity reduction. The proposed design supports the highest modulation schemes defined in IEEE Std. 802.15.3d, achieving an uncoded bit error rate of \u0000<inline-formula> <tex-math>$1.96times 10^{-4}$ </tex-math></inline-formula>\u0000 for 16-QAM and 64-QAM at SNRs of 18.8 dB and 25 dB, respectively. This meets the IEEE Std. 802.15.3d standard of \u0000<inline-formula> <tex-math>$10^{-12}$ </tex-math></inline-formula>\u0000 at SNRs of 19.6 dB and 25.6 dB for these modulation schemes after error correction. Our hardware operates at a clock rate of 1.76 GHz, enabling dual-stream transmission and achieving a throughput of 21.12 Gb/s with 64-QAM modulation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"14-25"},"PeriodicalIF":2.4,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10777587","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI 采用线性化动态放大器和输入缓冲器的22nm FDSOI节能管道sar ADC

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-03 DOI: 10.1109/OJCAS.2024.3509746

Bangda Yang;Trevor Caldwell;Anthony Chan Carusone

{"title":"An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI","authors":"Bangda Yang;Trevor Caldwell;Anthony Chan Carusone","doi":"10.1109/OJCAS.2024.3509746","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509746","url":null,"abstract":"Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"50-62"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10774063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training 流CNN的RFSoC调制分类：数据集生成和量化感知训练

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-03 DOI: 10.1109/OJCAS.2024.3509627

Andrew Maclellan;Louise H. Crockett;Robert W. Stewart

{"title":"RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training","authors":"Andrew Maclellan;Louise H. Crockett;Robert W. Stewart","doi":"10.1109/OJCAS.2024.3509627","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509627","url":null,"abstract":"This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"38-49"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772713","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications 有线应用中源退化差分对的线性分析

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-11-27 DOI: 10.1109/OJCAS.2024.3507543

Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone

引用次数: 0

A Generalized Active Voltage Balancing Circuit Implementation for Flying Capacitor 3-Level Switching-Mode DC–DC Converters 飞电容三电平开关模式 DC-DC 转换器的通用有源电压平衡电路实现方法

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-11-06 DOI: 10.1109/OJCAS.2024.3492320

Elisabetta Moisello;Samuele Fusetto;Piero Malcovati;Edoardo Bonizzoni

{"title":"A Generalized Active Voltage Balancing Circuit Implementation for Flying Capacitor 3-Level Switching-Mode DC–DC Converters","authors":"Elisabetta Moisello;Samuele Fusetto;Piero Malcovati;Edoardo Bonizzoni","doi":"10.1109/OJCAS.2024.3492320","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3492320","url":null,"abstract":"This paper presents a generalized control architecture for implementing the active balancing of the flying capacitor voltage in any kind of 3-level switching-mode DC-DC converters, independently from the desired conversion ratio or targeted output power level. The proposed strategy is based on the detection of the flying capacitor voltage through the inductor voltage, sensed at the switching node, and acts on the duty cycle of the PWM (Pulse Width Modulation) control signals in order to make the correction, implementing the voltage balancing. The circuit implementation and its operation are described in detail. Extensive simulations were performed in the SIMPLIS environment, taking as examples the cases of a 3-level buck, 3-level boost and 3-level inverting buck-boost DC-DC converter and considering different combinations of input voltage, output voltage and load current. Moreover, the proposed strategy was implemented in the control architecture of a hybrid switched-capacitor 3-level inverting buck-boost converter, fabricated in a 180-nm BCD process. The effectiveness and the versatility of the proposed active voltage balancing strategy and its circuit implementation were, therefore, verified both through simulations and experimentally.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"365-376"},"PeriodicalIF":2.4,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10745640","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142672080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation 基于数字本底线性校准的 DR 无损耗抖动技术，用于具有数字输入干扰消除功能的 SAR 辅助多级 ADC

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-10-28 DOI: 10.1109/OJCAS.2024.3486809

Lizhen Zhang;Bo Gao;Kun-Woo Park;Kent Edrian Lozada;Raymond Mabilangan;Hyeongjin Kim;Jianhui Wu;Seung-Tak Ryu

{"title":"DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation","authors":"Lizhen Zhang;Bo Gao;Kun-Woo Park;Kent Edrian Lozada;Raymond Mabilangan;Hyeongjin Kim;Jianhui Wu;Seung-Tak Ryu","doi":"10.1109/OJCAS.2024.3486809","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3486809","url":null,"abstract":"In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a \u0000<inline-formula> <tex-math>$50times $ </tex-math></inline-formula>\u0000 reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"349-364"},"PeriodicalIF":2.4,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736969","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142600215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling 带有重复使用的输入/输出接口和直流信号的小型防篡改、防回收集成电路传感器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-10-28 DOI: 10.1109/OJCAS.2024.3487072

Alexandros Dimopoulos;Mihai Sima;Stephen W. Neville

{"title":"A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling","authors":"Alexandros Dimopoulos;Mihai Sima;Stephen W. Neville","doi":"10.1109/OJCAS.2024.3487072","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3487072","url":null,"abstract":"Counterfeit electronic components are known to enter supply chains through recycling, with these already-aged components creating serious reliability risks, particularly for critical infrastructure systems. A number of recycled integrated circuit (IC) risk mitigation approaches have been proposed, but these generally lack pragmatic feasibility. This work proposes a novel real-world deployable on-chip sensor that: 1) is tamper-resistant by exploiting persistent changes caused by hot carrier injection (HCI); 2) generates a DC signal measurable by common low-cost test equipment; and 3) reuses an existing I/O interface, including existing pins; while 4) requiring a very small footprint. Combining this sensor with a random sample-based testing strategy allows for low-cost and time efficient detection of fraudulently recycled batches of ICs. Through simulation-based validation using process-accurate models of a 65 nm technology we show that employing a random sample size as small as 130 is sufficient for identifying such batches with a statistical significance level of 0.01.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"341-348"},"PeriodicalIF":2.4,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736936","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142600218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline 单元上的双 MAC：基于 22 纳米 8T-SRAM 的模拟内存加速器，用于二元/三元神经网络，具有分割字线功能

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-10-17 DOI: 10.1109/OJCAS.2024.3482469

Hiroto Tagata;Takashi Sato;Hiromitsu Awano

{"title":"Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline","authors":"Hiroto Tagata;Takashi Sato;Hiromitsu Awano","doi":"10.1109/OJCAS.2024.3482469","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3482469","url":null,"abstract":"This paper proposes a novel 8T-SRAM based computing-in-memory (CIM) accelerator for the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two input ports, simultaneously performing two binary multiply-and-accumulate (MAC) operations on left and right bitlines. This approach enables a twofold increase in throughput without significantly increasing area or power consumption, since the area overhead for doubling throughput is only two additional WL wires compared to the conventional 8T-SRAM. In addition, the proposed circuit supports binary and ternary activation input, allowing flexible adjustment of high energy efficiency and high inference accuracy depending on the application. The proposed SRAM macro consists of a \u0000<inline-formula> <tex-math>$128 times 128$ </tex-math></inline-formula>\u0000 SRAM array that outputs the MAC operation results of 96 binary/ternary inputs and \u0000<inline-formula> <tex-math>$96 times 128$ </tex-math></inline-formula>\u0000 binary weights as 1-5 bit digital values. The proposed circuit performance was evaluated by post-layout simulation with the 22-nm process layout of the overall CIM macro. The proposed circuit is capable of high-speed operation at 1 GHz. It achieves a maximum area efficiency of 3320 TOPS/mm2, which is \u0000<inline-formula> <tex-math>$3.4 times $ </tex-math></inline-formula>\u0000 higher compared to existing research with a reasonable energy efficiency of 1471 TOPS/W. The simulated inference accuracies of the proposed circuit are 96.45%/97.67% for MNIST dataset with binary/ternary MLP model, and 86.32%/88.56% for CIFAR-10 dataset with binary/ternary VGG-like CNN model.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"328-340"},"PeriodicalIF":2.4,"publicationDate":"2024-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10721281","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142579204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0