IEEE open journal of circuits and systems最新文献_第2页

2024 Index IEEE Open Journal of Circuits and Systems Vol. 5 IEEE电路与系统开放杂志第5卷

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-01-27 DOI: 10.1109/OJCAS.2025.3533978

引用次数: 0

IEEE Circuits and Systems Society 电路与系统学会

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-01-09 DOI: 10.1109/OJCAS.2025.3525785

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Analysis and Verilog-A Modeling of Floating-Gate Transistors 浮栅晶体管的分析与Verilog-A建模

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-31 DOI: 10.1109/OJCAS.2024.3524363

Sayma Nowshin Chowdhury;Matthew Chen;Sahil Shah

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IEEE Circuits and Systems Society 电路与系统学会

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-17 DOI: 10.1109/OJCAS.2024.3517215

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Instruction for Authors 作者须知

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-17 DOI: 10.1109/OJCAS.2024.3517219

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ASIC Current-Reuse Amplifier With MEMS Delta-E Magnetic Field Sensors 带MEMS Delta-E磁场传感器的ASIC电流复用放大器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-16 DOI: 10.1109/OJCAS.2024.3472124

Patrick Wiegand;Sebastian Simmich;Fatih Ilgaz;Franz Faupel;Benjamin Spetzler;Robert Rieger

{"title":"ASIC Current-Reuse Amplifier With MEMS Delta-E Magnetic Field Sensors","authors":"Patrick Wiegand;Sebastian Simmich;Fatih Ilgaz;Franz Faupel;Benjamin Spetzler;Robert Rieger","doi":"10.1109/OJCAS.2024.3472124","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3472124","url":null,"abstract":"An application specific integrated circuit (ASIC) and a custom-made microelectromechanical system (MEMS) sensor are presented, designed to function together as a sensor system for measuring low amplitude low frequency magnetic fields. The MEMS system comprises several free-standing double-wing magnetoelectric resonators with a size of \u0000<inline-formula> <tex-math>$900~mu $ </tex-math></inline-formula>\u0000m x \u0000<inline-formula> <tex-math>$150~mu $ </tex-math></inline-formula>\u0000m to measure alternating magnetic fields in the sub-kilohertz regime. It utilizes piezolelectric (AlN) and magnetostrictive (FeCoSiB) layers to exploit the delta-E effect for magnetic field sensing. On the ASIC a three-channel current-reuse amplifier with lateral bipolar transistors in the input stage is implemented occupying a chip area of 0.0864 mm2. Measurements demonstrate a voltage gain of 40 dB with a 3-dB bandwidth of 75 kHz and an input referred noise floor of 8 nV/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz while consuming \u0000<inline-formula> <tex-math>$199~mu $ </tex-math></inline-formula>\u0000W per channel. The sensor system is capable of detecting magnetic fields with a limit of detection (LOD) of 16 nT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz for single sensor elements. By operating three sensor elements in parallel, one on each amplifier channel, the LOD is further reduced to 10 nT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz. Owing to the high reproducibility of the sensor elements, this improvement in the LOD is close to the ideal value of \u0000<inline-formula> <tex-math>$surd 3$ </tex-math></inline-formula>\u0000. The results imply that the system can be scaled to large numbers of sensor elements without principle obstacles.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"398-407"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801234","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology 用于 22 纳米 FDSOI 技术低温性能评估的电压基准和稳压器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-16 DOI: 10.1109/OJCAS.2024.3466395

Alfonso R. Cabrera-Galicia;Arun Ashok;Patrick Vliex;Andre Kruth;André Zambanini;Stefan van Waasen

{"title":"Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology","authors":"Alfonso R. Cabrera-Galicia;Arun Ashok;Patrick Vliex;Andre Kruth;André Zambanini;Stefan van Waasen","doi":"10.1109/OJCAS.2024.3466395","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3466395","url":null,"abstract":"This paper presents the design and cryogenic electrical characterization of a voltage reference and a linear voltage regulator at temperatures between 6 K and 300 K. Both circuits are employed as test vehicles for the experimental performance evaluation of the 22 nm FDSOI MOS technology when used as platform for the development of cryogenic analog systems, whose role is relevant in Quantum Computing (QC) applications. Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. In particular, we focus on the cryogenic threshold voltage \u0000<inline-formula> <tex-math>$(V_{text {th}})$ </tex-math></inline-formula>\u0000 saturation, the transconductance \u0000<inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula>\u0000 increase and the low frequency (LF) excess noise. Our experimental results indicate that the cryogenic \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 saturation and the \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000 increase can be used as circuit design tools, while the LF excess noise is a performance handicap for cryogenic analog circuits.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"377-386"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801233","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation V2Va +：用于加速混合信号仿真的高效 SystemVerilog 和 Verilog-to-Verilog-A 转换器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-16 DOI: 10.1109/OJCAS.2024.3451530

Chao Wang;Yicong Shao;Jiajie Huang;Wangzilu Lu;Zhiwen Gu;Longfan Li;Yuhang Zhang;Jian Zhao;Wei Mao;Yongfu Li

{"title":"V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation","authors":"Chao Wang;Yicong Shao;Jiajie Huang;Wangzilu Lu;Zhiwen Gu;Longfan Li;Yuhang Zhang;Jian Zhao;Wei Mao;Yongfu Li","doi":"10.1109/OJCAS.2024.3451530","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3451530","url":null,"abstract":"This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over \u0000<inline-formula> <tex-math>$2{times }$ </tex-math></inline-formula>\u0000. These strengths underscore its significant impact and applicability in the domain of circuit design.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"387-397"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability 一种具有类cpu可编程性的高能效顺序可重构阵列

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-16 DOI: 10.1109/OJCAS.2024.3518110

Tobias Kaiser;Esther Gottschalk;Kai Biethahn;Friedel Gerfers

{"title":"Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability","authors":"Tobias Kaiser;Esther Gottschalk;Kai Biethahn;Friedel Gerfers","doi":"10.1109/OJCAS.2024.3518110","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3518110","url":null,"abstract":"This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"1-13"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10802954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model 亚太赫兹信道模型下多流MIMO系统的同步与信道估计设计

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-04 DOI: 10.1109/OJCAS.2024.3510921

Chung-Lun Tu;Chen-Yuan Tseng;Wei-Che Lee;Kang-Lun Chiu;Pei-Yun Tsai;Shyh-Jye Jou

{"title":"Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model","authors":"Chung-Lun Tu;Chen-Yuan Tseng;Wei-Che Lee;Kang-Lun Chiu;Pei-Yun Tsai;Shyh-Jye Jou","doi":"10.1109/OJCAS.2024.3510921","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3510921","url":null,"abstract":"This article presents an advanced synchronization and channel estimation architecture for multi-stream MIMO systems in sub-terahertz environments. To streamline hardware complexity, we employ Golay cross-correlation across all detection and estimation schemes. Key innovations include a precise timing detection algorithm that utilizes pulse shaping impulse response and quadratic regression, along with multiple window-based approaches to enhance performance against non-ideal effects. At the architectural level, a shared optimized Golay correlator reduces hardware usage by 23%, efficiently handling multiple correlation lengths in a single design. Additionally, we propose an indexing-count method that addresses sorting challenges, achieving notable improvements in processing speed and complexity reduction. The proposed design supports the highest modulation schemes defined in IEEE Std. 802.15.3d, achieving an uncoded bit error rate of \u0000<inline-formula> <tex-math>$1.96times 10^{-4}$ </tex-math></inline-formula>\u0000 for 16-QAM and 64-QAM at SNRs of 18.8 dB and 25 dB, respectively. This meets the IEEE Std. 802.15.3d standard of \u0000<inline-formula> <tex-math>$10^{-12}$ </tex-math></inline-formula>\u0000 at SNRs of 19.6 dB and 25.6 dB for these modulation schemes after error correction. Our hardware operates at a clock rate of 1.76 GHz, enabling dual-stream transmission and achieving a throughput of 21.12 Gb/s with 64-QAM modulation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"14-25"},"PeriodicalIF":2.4,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10777587","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0