Sai Sanjeet;Sanchari Das;Shiuh-Hua Wood Chiang;Masahiro Fujita;Bibhu Datta Datta
{"title":"基于环形vco的snn转换训练参数到电路的系统设计","authors":"Sai Sanjeet;Sanchari Das;Shiuh-Hua Wood Chiang;Masahiro Fujita;Bibhu Datta Datta","doi":"10.1109/OJCAS.2025.3585654","DOIUrl":null,"url":null,"abstract":"The deployment of digitally-trained analog Spiking Neural Networks (SNNs) presents a promising approach for energy-efficient edge computing. However, training such networks is not trivial, and discrepancies between digital training models and their continuous-time analog implementations pose challenges in validation and performance verification. This paper aims to bridge the gap between the design of analog neuron models and training SNNs with the neuron model, along with a time-domain verification framework that enables circuit designers to validate their analog SNN implementations in a simulation environment resembling industry-standard EDA tools such as Cadence and Synopsys while offering significantly faster execution. This work focuses on a ring oscillator-based neuron model, which realizes the leaky integrate-and-fire (LIF) neuron. The design of the ring oscillator-based neuron is discussed, and the neuron model is digitized using the bilinear transform to enable training. The trained network is used to classify the MNIST dataset with an accuracy of 97.35% and the Iris dataset with an accuracy of 93.33%. We further introduce a time-domain verification framework based on Simulink to validate the trained networks. We verify our approach by comparing digitally-trained PyTorch models against analog implementations simulated using our framework on the Iris dataset, revealing accuracy discrepancies between the analog and digital counterparts, along with insights into the cause of such discrepancies, which would have been difficult to simulate with SPICE simulators. Additionally, we verify the generated Simulink models against Verilog-A models simulated in Cadence Spectre, demonstrating that our framework produces identical outputs while achieving an order-of-magnitude speedup. By providing an efficient, accurate, and accessible verification platform, our framework bridges the gap between digital training and analog hardware verification, facilitating the development of robust, high-performance SNNs for edge applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"283-294"},"PeriodicalIF":2.4000,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106930","citationCount":"0","resultStr":"{\"title\":\"Systematic Design of Ring VCO-Based SNN—Translating Training Parameters to Circuits\",\"authors\":\"Sai Sanjeet;Sanchari Das;Shiuh-Hua Wood Chiang;Masahiro Fujita;Bibhu Datta Datta\",\"doi\":\"10.1109/OJCAS.2025.3585654\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The deployment of digitally-trained analog Spiking Neural Networks (SNNs) presents a promising approach for energy-efficient edge computing. However, training such networks is not trivial, and discrepancies between digital training models and their continuous-time analog implementations pose challenges in validation and performance verification. This paper aims to bridge the gap between the design of analog neuron models and training SNNs with the neuron model, along with a time-domain verification framework that enables circuit designers to validate their analog SNN implementations in a simulation environment resembling industry-standard EDA tools such as Cadence and Synopsys while offering significantly faster execution. This work focuses on a ring oscillator-based neuron model, which realizes the leaky integrate-and-fire (LIF) neuron. The design of the ring oscillator-based neuron is discussed, and the neuron model is digitized using the bilinear transform to enable training. The trained network is used to classify the MNIST dataset with an accuracy of 97.35% and the Iris dataset with an accuracy of 93.33%. We further introduce a time-domain verification framework based on Simulink to validate the trained networks. We verify our approach by comparing digitally-trained PyTorch models against analog implementations simulated using our framework on the Iris dataset, revealing accuracy discrepancies between the analog and digital counterparts, along with insights into the cause of such discrepancies, which would have been difficult to simulate with SPICE simulators. Additionally, we verify the generated Simulink models against Verilog-A models simulated in Cadence Spectre, demonstrating that our framework produces identical outputs while achieving an order-of-magnitude speedup. By providing an efficient, accurate, and accessible verification platform, our framework bridges the gap between digital training and analog hardware verification, facilitating the development of robust, high-performance SNNs for edge applications.\",\"PeriodicalId\":93442,\"journal\":{\"name\":\"IEEE open journal of circuits and systems\",\"volume\":\"6 \",\"pages\":\"283-294\"},\"PeriodicalIF\":2.4000,\"publicationDate\":\"2025-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106930\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE open journal of circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11106930/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE open journal of circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11106930/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Systematic Design of Ring VCO-Based SNN—Translating Training Parameters to Circuits
The deployment of digitally-trained analog Spiking Neural Networks (SNNs) presents a promising approach for energy-efficient edge computing. However, training such networks is not trivial, and discrepancies between digital training models and their continuous-time analog implementations pose challenges in validation and performance verification. This paper aims to bridge the gap between the design of analog neuron models and training SNNs with the neuron model, along with a time-domain verification framework that enables circuit designers to validate their analog SNN implementations in a simulation environment resembling industry-standard EDA tools such as Cadence and Synopsys while offering significantly faster execution. This work focuses on a ring oscillator-based neuron model, which realizes the leaky integrate-and-fire (LIF) neuron. The design of the ring oscillator-based neuron is discussed, and the neuron model is digitized using the bilinear transform to enable training. The trained network is used to classify the MNIST dataset with an accuracy of 97.35% and the Iris dataset with an accuracy of 93.33%. We further introduce a time-domain verification framework based on Simulink to validate the trained networks. We verify our approach by comparing digitally-trained PyTorch models against analog implementations simulated using our framework on the Iris dataset, revealing accuracy discrepancies between the analog and digital counterparts, along with insights into the cause of such discrepancies, which would have been difficult to simulate with SPICE simulators. Additionally, we verify the generated Simulink models against Verilog-A models simulated in Cadence Spectre, demonstrating that our framework produces identical outputs while achieving an order-of-magnitude speedup. By providing an efficient, accurate, and accessible verification platform, our framework bridges the gap between digital training and analog hardware verification, facilitating the development of robust, high-performance SNNs for edge applications.