Systematic Design of Ring VCO-Based SNN—Translating Training Parameters to Circuits

IF 2.4 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Sai Sanjeet;Sanchari Das;Shiuh-Hua Wood Chiang;Masahiro Fujita;Bibhu Datta Datta
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Abstract

The deployment of digitally-trained analog Spiking Neural Networks (SNNs) presents a promising approach for energy-efficient edge computing. However, training such networks is not trivial, and discrepancies between digital training models and their continuous-time analog implementations pose challenges in validation and performance verification. This paper aims to bridge the gap between the design of analog neuron models and training SNNs with the neuron model, along with a time-domain verification framework that enables circuit designers to validate their analog SNN implementations in a simulation environment resembling industry-standard EDA tools such as Cadence and Synopsys while offering significantly faster execution. This work focuses on a ring oscillator-based neuron model, which realizes the leaky integrate-and-fire (LIF) neuron. The design of the ring oscillator-based neuron is discussed, and the neuron model is digitized using the bilinear transform to enable training. The trained network is used to classify the MNIST dataset with an accuracy of 97.35% and the Iris dataset with an accuracy of 93.33%. We further introduce a time-domain verification framework based on Simulink to validate the trained networks. We verify our approach by comparing digitally-trained PyTorch models against analog implementations simulated using our framework on the Iris dataset, revealing accuracy discrepancies between the analog and digital counterparts, along with insights into the cause of such discrepancies, which would have been difficult to simulate with SPICE simulators. Additionally, we verify the generated Simulink models against Verilog-A models simulated in Cadence Spectre, demonstrating that our framework produces identical outputs while achieving an order-of-magnitude speedup. By providing an efficient, accurate, and accessible verification platform, our framework bridges the gap between digital training and analog hardware verification, facilitating the development of robust, high-performance SNNs for edge applications.
基于环形vco的snn转换训练参数到电路的系统设计
数字训练的模拟峰值神经网络(snn)的部署为节能边缘计算提供了一种有前途的方法。然而,训练这样的网络并非易事,数字训练模型与其连续时间模拟实现之间的差异给验证和性能验证带来了挑战。本文旨在弥合模拟神经元模型设计与使用神经元模型训练SNN之间的差距,以及一个时域验证框架,使电路设计人员能够在类似于Cadence和Synopsys等行业标准EDA工具的仿真环境中验证其模拟SNN实现,同时提供显着更快的执行速度。本文研究了一种基于环振子的神经元模型,该模型实现了漏失集成点火(LIF)神经元。讨论了基于环振的神经元的设计,并利用双线性变换对神经元模型进行了数字化处理,使训练成为可能。使用训练好的网络对MNIST数据集和Iris数据集进行分类,分类准确率分别为97.35%和93.33%。我们进一步介绍了一个基于Simulink的时域验证框架来验证训练好的网络。我们通过比较数字训练的PyTorch模型与使用Iris数据集上的框架模拟的模拟实现来验证我们的方法,揭示了模拟和数字对应物之间的准确性差异,以及对这种差异原因的见解,这将很难用SPICE模拟器模拟。此外,我们针对Cadence Spectre中模拟的Verilog-A模型验证了生成的Simulink模型,证明我们的框架在实现数量级加速的同时产生相同的输出。通过提供高效,准确和可访问的验证平台,我们的框架弥合了数字训练和模拟硬件验证之间的差距,促进了边缘应用的强大,高性能snn的开发。
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