IEEE open journal of circuits and systems最新文献

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Filters With Gamma Kernel Impulse Response: Realization and Application in Auditory Systems 具有伽玛核脉冲响应的滤波器:在听觉系统中的实现与应用
IF 1.8
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-06-25 DOI: 10.1109/OJCAS.2026.3707171
Julia Nako;Georgia Tsirimokou;Costas Psychalinos;Ahmed S. Elwakil
{"title":"Filters With Gamma Kernel Impulse Response: Realization and Application in Auditory Systems","authors":"Julia Nako;Georgia Tsirimokou;Costas Psychalinos;Ahmed S. Elwakil","doi":"10.1109/OJCAS.2026.3707171","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3707171","url":null,"abstract":"This paper presents a unified and flexible framework for implementing auditory-inspired filters based on the Gamma Kernel. The proposed structure enables both Gammatone and Gammachirp filters to be realized using the same configuration, providing a compact and versatile design suitable for auditory modeling and signal processing applications. This is achieved through the utilization of a curve-fitting technique in MATLAB that approximates the Laplace transform of each filter’s impulse response, leading to a rational integer-order transfer function. By adjusting the coefficient values of this function both Gammatone and Gammachirp filter-banks can be implemented, significantly simplifying the design and tuning process. An auditory filter example implemented on a Field Programmable Analog Array (FPAA) device is demonstrated, where magnitude and impulse responses are both evaluated.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"396-403"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11579389","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis of Lossless Multiports as Minimum Depth Chessboard Networks 无损多端口最小深度棋盘网络的综合
IF 1.8
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-07-10 DOI: 10.1109/OJCAS.2026.3712274
Piero Angeletti;Antonio Morini;Antoine Roederer;Giovanni Toso
{"title":"Synthesis of Lossless Multiports as Minimum Depth Chessboard Networks","authors":"Piero Angeletti;Antonio Morini;Antoine Roederer;Giovanni Toso","doi":"10.1109/OJCAS.2026.3712274","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3712274","url":null,"abstract":"The synthesis of lossless multiport networks is a classic topic of circuit theory, with broad application in various signal distribution and processing systems. This paper presents a method for synthesizing reciprocal lossless <inline-formula> <tex-math>$N$ </tex-math></inline-formula>-port networks with an assigned scattering matrix, and reciprocal lossless matched and decoupled <inline-formula> <tex-math>$2N$ </tex-math></inline-formula>-port networks with an assigned transmission matrix, as minimum depth chessboard networks. The proposed approach leverages bilateral factorization techniques, extending existing reductive methods by incorporating a new degree of freedom in the selection process. The resulting chessboard network configuration minimizes network depth and component count, offering improved uniformity in input-output paths. Theoretical findings are validated through numerical implementations, demonstrating high accuracy and stability. This method provides a compact and efficient solution for designing reciprocal lossless multiport networks, with significant potential for applications in diverse fields requiring robust and efficient network architectures.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"447-464"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11603393","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148749030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Tunable 1.3–2.1-GHz Parametric Notch Filtering on GaAs MMIC With Double Pump Q-Enhancement 双泵浦增q的GaAs MMIC可调谐1.3 - 2.1 ghz参数陷波滤波
IF 1.8
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-08-06 DOI: 10.1109/OJCAS.2026.3719853
Sean C. Chen;Lap K. Yeung;Yan Jean Wei;Keith Runge;Pierre A. Deymier;Yuanxun Ethan Wang
{"title":"Tunable 1.3–2.1-GHz Parametric Notch Filtering on GaAs MMIC With Double Pump Q-Enhancement","authors":"Sean C. Chen;Lap K. Yeung;Yan Jean Wei;Keith Runge;Pierre A. Deymier;Yuanxun Ethan Wang","doi":"10.1109/OJCAS.2026.3719853","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3719853","url":null,"abstract":"This paper presents a tunable parametric notch filter based on a double-pump parametric-mixing architecture that enables on-chip Q-enhancement. A primary pump generates a frequency-dependent positive conductance at the signal frequency, producing a tunable absorption notch, while a secondary pump introduces negative resistance at the idler frequency to compensate resonator loss and enhance selectivity. This mechanism, referred to as parametric mixing, enables active control of the effective quality factor of the idler resonance without external high-Q components. The proposed architecture is implemented as a fully integrated GaAs MMIC and operates over a tuning range of 1.3-2.1 GHz. Measurements show that single-pump operation produces a tunable notch with 4.5-6 dB attenuation, while activation of the second pump increases the notch depth to 13.5-25 dB and reduces the fractional bandwidth to 5.5-6.5%, consistent with Q-enhanced behavior. The device also exhibits a low-loss through response when both pumps are disabled, enabling a true notch-off state. Measured S-parameters show that the double-pump operation substantially improves notch depth and fractional bandwidth, while simulation-based effective-Q extraction supports the interpretation that this improvement results from idler loss compensation, providing a compact and scalable solution for high-selectivity reconfigurable RF filtering.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"479-489"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11643804","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148781062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Gain, Low-Voltage Operational Amplifier With Bias-Stress and PVT Robustness for Large-Area Temperature Sensing on LTPS Substrates 一种用于LTPS基板上大面积温度传感的高增益、低压偏置应力和PVT鲁棒运算放大器
IF 2.4
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2025-12-19 DOI: 10.1109/OJCAS.2025.3631308
Chen Wang;Xiaonan Xing;Seyed Mojtaba Sadati Faramarzi;Aris Siskos;Qiuyang Lin;Yannick Baines;Chutham Sawigun;Mauricio Velazquez Lopez;Florian De Roose;Jan Genoe;Nikolas Papadopoulos;Kris Myny
{"title":"A High-Gain, Low-Voltage Operational Amplifier With Bias-Stress and PVT Robustness for Large-Area Temperature Sensing on LTPS Substrates","authors":"Chen Wang;Xiaonan Xing;Seyed Mojtaba Sadati Faramarzi;Aris Siskos;Qiuyang Lin;Yannick Baines;Chutham Sawigun;Mauricio Velazquez Lopez;Florian De Roose;Jan Genoe;Nikolas Papadopoulos;Kris Myny","doi":"10.1109/OJCAS.2025.3631308","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3631308","url":null,"abstract":"This paper analyzes the temperature coefficients of low temperature polysilicon (LTPS) devices and investigates critical blocks of a system architecture for large-area temperature sensing, which integrates sensors and readout circuits monolithically. As part of this system, a low-voltage folded-cascode (LV-FC) operational amplifier (OpAmp) with a class-AB output stage was designed and implemented using an LTPS thin film transistor (TFT) process on a 15 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick polyimide flexible substrate. The performance of 20 amplifier samples was thoroughly characterized under DC, AC, long-term bias-stress (up to 40,000 seconds), and temperature conditions (0 °C to 80 °C). The amplifier achieves a maximum DC gain of 64.2 dB and a gain-bandwidth product of 400 kHz, while operating reliably under a 6 V supply with a peak power consumption of 0.6 mW in a compact area of 1.38 mm2. Under bias stress, the gain degraded by only 2.5 dB and the offset shifted by 1.5 mV. Over the full temperature range, the average gain varied by less than 2 dB and the offset by under 6 mV. These results demonstrate strong robustness against PVT variations and prolonged stress, confirming the suitability of the proposed LV-FC amplifier for flexible, long-term, and large-area temperature sensing applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"230-242"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Single-Ended SAR ADC With Energy-Efficient Differential Switching for Ultrafast X-Ray Imagers 一种用于超快x射线成像仪的低功耗单端差分开关SAR ADC
IF 2.4
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2025-12-19 DOI: 10.1109/OJCAS.2025.3628857
Aldo Pena-Perez;Hugo Hernandez-Herrera;Llorenç Fanals-I-Batllori;Lorenzo Rota;Hyunjoon Kim;Aseem Gupta;Bojan Markovic;Gang Liu;Filippo Mele;Pietro King;Christos Bakalis;Dionisio Doering;Namit Mishra;Angelo Dragone
{"title":"A Low-Power Single-Ended SAR ADC With Energy-Efficient Differential Switching for Ultrafast X-Ray Imagers","authors":"Aldo Pena-Perez;Hugo Hernandez-Herrera;Llorenç Fanals-I-Batllori;Lorenzo Rota;Hyunjoon Kim;Aseem Gupta;Bojan Markovic;Gang Liu;Filippo Mele;Pietro King;Christos Bakalis;Dionisio Doering;Namit Mishra;Angelo Dragone","doi":"10.1109/OJCAS.2025.3628857","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3628857","url":null,"abstract":"This work presents a SAR ADC architecture designed for single-ended-to-differential conversion with low-energy switching and area efficiency. By incorporating top and bottom sampling techniques, the architecture achieves seamless conversion without the need for extra DAC hardware. It offers configurable fully-differential or single-ended modes by means of <inline-formula> <tex-math>$V_{text {cm}}$ </tex-math></inline-formula>-based switching. With 75 % reduced total capacitance compared to the conventional method, consistent energy savings are achieved across configurations. Implemented in <inline-formula> <tex-math>$mathrm {130~nm }$ </tex-math></inline-formula> CMOS, this design features an array of 48 ADCs and custom on-chip voltage references integrated within the SparkPix-S ASIC, a device tailored for X-ray imagers. With a nominal sampling rate of 5 MSps and <inline-formula> <tex-math>$mathrm {1.2~V }$ </tex-math></inline-formula> supply voltage, the achieved SNDR is 54.5 dB, with <inline-formula> <tex-math>$+0.98/-0.86$ </tex-math></inline-formula> LSB of DNL and <inline-formula> <tex-math>$+0.83/-1.26$ </tex-math></inline-formula> LSB of INL. The core SAR ADC average power consumption is <inline-formula> <tex-math>$mathrm {96~uW }$ </tex-math></inline-formula>, resulting in a FOM of 40.1 dJ/conv-step, all within a compact active area of <inline-formula> <tex-math>$mathrm {0.0212~mm ^{2} }$ </tex-math></inline-formula>.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"255-268"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304255","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modulation Bandwidth Investigation of Voltage-Controlled Oscillators Under Periodic Linear Frequency Modulation 周期线性调频下压控振荡器的调制带宽研究
IF 2.4
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2025-12-18 DOI: 10.1109/OJCAS.2025.3606876
Rabia Fatima Riaz;Ronny Henker;Frank Ellinger
{"title":"Modulation Bandwidth Investigation of Voltage-Controlled Oscillators Under Periodic Linear Frequency Modulation","authors":"Rabia Fatima Riaz;Ronny Henker;Frank Ellinger","doi":"10.1109/OJCAS.2025.3606876","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3606876","url":null,"abstract":"The modulation bandwidth of a voltage-controlled oscillator (VCO) is a key design metric that defines its ability to respond to fast tuning voltages and change its frequency accordingly. While prior works have addressed practical methods for measuring it, particularly under sinusoidal excitation, the accuracy of these methods decreases for wideband VCOs due to their inherently nonlinear tuning behavior (i.e., non-constant tuning sensitivity). Our previous work focused on characterizing this bandwidth using periodic linear voltage excitation and presented only measurement results. The current paper significantly extends that study in three major ways. First, we apply FM theory to derive analytical expressions relating the modulation bandwidth to the tuning sensitivity and characteristics of the modulating waveform (i.e., periodic linear voltage excitation). This provides a theoretical framework for understanding the VCO’s behavior under non-sinusoidal excitations which are common in systems such as frequency-hopping transceivers, spread-spectrum clocking, certain phase-locked loops, and FMCW radars. These expressions confirm the dependence of the modulation bandwidth on the tuning sensitivity, VCO linearity and amplitude of the modulating waveform and help guide VCO design for fast signal excitations at the tuning port. Second, we present post-layout simulation results which agree with both theory and measurements, confirming the accuracy of the derived expressions. Third, we present more comprehensive comparisons with recent K-band SiGe BiCMOS VCOs to benchmark this work against state-of-the-art designs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"243-254"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304254","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
9.4 μW 285 Samples/s Capacitance to Digital Converter for Large Area Active EWOD Arrays in Thin-Film Transistor Technology 薄膜晶体管技术中大面积有源EWOD阵列的9.4 μ w285采样数变换器
IF 2.4
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-04-27 DOI: 10.1109/OJCAS.2026.3670665
Mauricio Velazquez Lopez;Nikolas Papadopoulos;Francois Berghmans;Kris Myny
{"title":"9.4 μW 285 Samples/s Capacitance to Digital Converter for Large Area Active EWOD Arrays in Thin-Film Transistor Technology","authors":"Mauricio Velazquez Lopez;Nikolas Papadopoulos;Francois Berghmans;Kris Myny","doi":"10.1109/OJCAS.2026.3670665","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3670665","url":null,"abstract":"This work introduces a low-power, linear-in-log capacitance sensing circuit tailored for large-area electrowetting-on-dielectric (EWOD) arrays utilizing thin-film transistor (TFT) technology. By leveraging the intrinsic time constants of the circuit, the proposed approach achieves enhanced sensitivity at low capacitance levels, effectively addressing scenarios where the EWOD electrode capacitance is on par with parasitic capacitances present in the system. Fabricated using a <inline-formula> <tex-math>$4.5~mu $ </tex-math></inline-formula>m Low Temperature Polysilicon (LTPS) TFT process, the circuit demonstrates up to 6-bit resolution, corresponding to 63 distinct measured capacitance levels, and measures capacitance variations as small as 61.3 fF. Two circuit variants are presented: the first, employing a one-transistor–one-resistor (1T1R) input stage, which operates at a peak/mean power consumption of <inline-formula> <tex-math>$16~mu $ </tex-math></inline-formula>W / <inline-formula> <tex-math>$3.0~mu $ </tex-math></inline-formula>W and occupies <inline-formula> <tex-math>$324times 324~mu $ </tex-math></inline-formula>m2; the second, incorporating a current mirror (CM) input stage, consumes <inline-formula> <tex-math>$35~mu $ </tex-math></inline-formula>W / <inline-formula> <tex-math>$9.4~mu $ </tex-math></inline-formula>W with an area of <inline-formula> <tex-math>$317times 506~mu $ </tex-math></inline-formula>m2. Both implementations mark a significant improvement in resolution, sensitivity and power efficiency compared to the current state-of-the-art in TFT technology.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"173-183"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11495347","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Feedforward Cancellation of Third-Order Nonlinear Distortion in Wideband Receivers 宽带接收机三阶非线性失真的前馈消除
IF 2.4
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-03-24 DOI: 10.1109/OJCAS.2026.3677259
Won Namgoong
{"title":"On Feedforward Cancellation of Third-Order Nonlinear Distortion in Wideband Receivers","authors":"Won Namgoong","doi":"10.1109/OJCAS.2026.3677259","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3677259","url":null,"abstract":"While many techniques have been proposed to improve receiver linearity, feedforward cancellation is especially attractive because it operates at the system level and complements circuit-level linearization, enabling additional performance gains. This paper analyzes the effectiveness of feedforward cancellation in the presence of multiple and/or broadband blockers, as commonly encountered in wireless environments. A Volterra-series receiver model is used to capture both nonlinear behavior and wideband memory effects. The analysis shows that robust suppression of third-order intermodulation distortion requires maintaining an approximately constant ratio between the relevant Volterra kernels of the main and auxiliary paths across frequency. Guided by this result, we present a feedforward cancellation architecture that employs nominally identical main and auxiliary paths to promote consistent kernel ratios. Experimental results validate the analysis and demonstrate that reducing kernel-ratio variations leads to significant improvements in receiver linearity.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"119-131"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11455224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A PPWM-Based CMOS Wireless Power Charger With Active Bias-Clamp Cascode Biasing and Load-Adaptive Rectifier Sizing 一种基于ppwm的有源偏置箝位级联偏置和负载自适应整流器尺寸的CMOS无线充电器
IF 2.4
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-03-24 DOI: 10.1109/OJCAS.2026.3676921
Chih-Man Chang;Kea-Tiong Tang
{"title":"A PPWM-Based CMOS Wireless Power Charger With Active Bias-Clamp Cascode Biasing and Load-Adaptive Rectifier Sizing","authors":"Chih-Man Chang;Kea-Tiong Tang","doi":"10.1109/OJCAS.2026.3676921","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3676921","url":null,"abstract":"This paper presents a wireless charging system for implantable medical devices, implemented in TSMC 0.18 um 1P6M CMOS and operating at 6.78 MHz with a single resonant coil pair. The proposed system supports a battery charging voltage range of <inline-formula> <tex-math>$2.6sim 4.2$ </tex-math></inline-formula> V, covering trickle-charge (TC), constant-current (CC), constant-voltage (CV), and direct power (DP) modes. The charger provides a constant output current ranging from 5 mA to 50 mA. The overall system achieves a peak efficiency of 88.9 %. The Active Bias-Clamp Cascode scheme is introduced to suppress over-voltage stress while significantly reducing the required bias capacitance, while the Load-Adaptive Rectifier Sizing (LARS) technique dynamically adjusts the rectifier conduction channel size according to load conditions. These techniques together improve efficiency and ensure robust operation across wide load variations, making the system well suited for highly constrained implantable applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"132-143"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11455212","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cost-Effective and Space-Saving AC/DC Solid-State Relay Without Potential Separation 具有成本效益和节省空间的交流/直流固态继电器无电位分离
IF 1.8
IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-06-08 DOI: 10.1109/OJCAS.2026.3701095
Wenzel Maier;Amilcar Flamarion Querubini Gonçalves;Ricardo Quadros Machado
{"title":"Cost-Effective and Space-Saving AC/DC Solid-State Relay Without Potential Separation","authors":"Wenzel Maier;Amilcar Flamarion Querubini Gonçalves;Ricardo Quadros Machado","doi":"10.1109/OJCAS.2026.3701095","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3701095","url":null,"abstract":"By design, solid-state relays are not subject to mechanical wear, exhibit no contact bounce or arcing, and are immune to shock and vibration. These properties enable their replacement of electromechanical relays in many applications. However, to fully exploit their potential, semiconductor-based relays must continue to be improved in terms of cost, area, and performance. This paper presents the functionality and structure of a low-cost solid-state relay. Two n-channel MOSFETs connected in anti-series are used as power switches, with their common gates driven by a “constant-current-injection” (CCI) control scheme. The resulting bidirectional semiconductor switch provides no galvanic isolation between the control and power stages, enabling a cost-efficient and space-saving solution. The proposed circuit is simple to implement, based on readily available components, and flexibly scalable in terms of current, voltage, and switching speed. In addition to the circuit description and the turn-on and turn-off behavior, a prototype implementation of the bidirectional relay is presented, which is targeted for cell selection in active battery management systems.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"366-377"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11554297","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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