IEEE open journal of circuits and systems最新文献

{"title":"A Ping-Pong Integrating FFE for Wireline SerDes Applications","authors":"Alireza Akbarpour Bazargani;Hossein Shakiba;David A. Johns","doi":"10.1109/OJCAS.2026.3699461","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3699461","url":null,"abstract":"This paper presents a ping-pong current-integrating feed-forward equalizer (PPI-FFE) architecture for high-speed wireline receivers, enabling the realization of multi-tap analog FFE with reduced hardware complexity. By leveraging time-interleaved integration and ping-pong operation, the proposed architecture decouples the number of FFE taps from the number of first-rank track-and-hold (T/H), significantly reducing the required number of jitter- and skew-sensitive sampling elements and unit Gm-cells compared to conventional interleaved discrete-time FFE implementations. As a result, the architecture offers a more compact and routing-friendly solution, mitigating parasitic and matching challenges in analog FFE design. As a proof of concept, a reconfigurable 4-tap PPI-FFE is implemented in 22-nm FDSOI technology targeting a 112-Gb/s PAM-4 receiver. Post-layout simulation results demonstrate effective ISI mitigation over a 32-dB-loss channel at Nyquist, with 26 mW power consumption for the core FFE and clock generation circuitry. Comparison with recent mixed-mode receivers shows superior area and power efficiency for the core FFE functionality.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"308-318"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11547203","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual-Band Matching Topologies for mmWave Circuits Demonstrated on a 79/135 GHz Dual-Mode Power Amplifier in 28-nm Bulk CMOS","authors":"Yiqin Hou;Florent Kirkels;Rainier van Dommele;Dusan Milosevic;Vojkan Vidojkovic","doi":"10.1109/OJCAS.2026.3734036","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3734036","url":null,"abstract":"This paper investigates dual-band matching (DBM) topologies for mmWave circuits, with emphasis on double-tuned transformers and resonator-coupled inductors. An approximate analytical model of a double-tuned transformer is developed to provide physical insight and enable efficient initial design for DBM, reducing the need for brute-force parameter sweeps. To overcome the limitations of transformer-based matching of a fixed transformation ratio across frequencies, a resonator-coupled inductor is proposed. It offers frequency-dependent inductance with lower effective inductance at higher frequencies, enabling dual-band operation, without requiring extra area compared to conventional inductors. The concepts are validated using a 79/135 GHz dual-mode three-stage power amplifier (PA) implemented in 28-nm bulk CMOS with joint active–passive co-design. At the operating frequency of 79 GHz, it provides 23 dB power gain, 8.7 dBm output 1-dB compression point (<inline-formula> <tex-math>$P_{mathrm {1dB}}$ </tex-math></inline-formula>), 11.1 dBm saturated output power (<inline-formula> <tex-math>$P_{mathrm {sat}}$ </tex-math></inline-formula>) with a peak power added efficiency (<inline-formula> <tex-math>$mathrm {PAE}_{max }$ </tex-math></inline-formula>) of 12.4%. At 135 GHz, the measured power gain is 11.5 dB, achieved <inline-formula> <tex-math>$P_{mathrm {1dB}}$ </tex-math></inline-formula> is 3.9 dBm. <inline-formula> <tex-math>$P_{mathrm {sat}}$ </tex-math></inline-formula> is 9.5 dBm with <inline-formula> <tex-math>$mathrm {PAE}_{max }$ </tex-math></inline-formula> of 5.9%. The E-band performance is comparable to state-of-the-art designs, while modest degradation in D-band arises from dual-mode trade-offs and the use of a conventional common-source topology. These results confirm the effectiveness of the proposed DBM approaches for practical dual-band mmWave operation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"531-542"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11695232","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149131589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chaotic Circuit Design Leveraging the Analog Nonlinear Dynamics of a Self-Rectifying Memristor","authors":"Xianyue Zhao;Alon Ascoli;Ahmet Samil Demirkol;Ioannis Messaris;Jan Dellith;Ilia Polian;Heidemarie Krüger;Ronald Tetzlaff;Nan Du","doi":"10.1109/OJCAS.2025.3648317","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3648317","url":null,"abstract":"Memristive devices have attracted significant attention due to their intrinsic nonlinearity, memory-dependent behavior, and ability to encode information through continuously tunable resistive states at the nanoscale. Beyond its use in non-volatile memories and neuromorphic architecture, the memristor is increasingly investigated for chaotic and nonlinear circuit design, where its analog hysteretic response can enable compact and energy-efficient chaotic systems. To date, memristor-based chaotic circuit designs have predominantly focused on binary (abrupt-switching) devices, while analog (gradual-switching) memristors, despite their advantages such as low operating current and high reproducibility, have not yet been explored for their potential to generate and sustain chaotic behavior. In this work, we use a self-rectifying BiFeO3 (BFO) memristor as a demonstrator to investigate how analog nonlinear dynamics can be harnessed for chaotic RC oscillator design. Based on experimental characterization of its frequency-dependent response, a physically grounded behavioral model is developed to accurately capture the device’s analog and self-rectifying characteristics, showing excellent agreement with measured data. Using this model, we adapt a low-frequency third-order RC chaotic circuit from the literature by replacing its diode with the BFO memristor and its parasitic capacitance, where the BFO device serves as the single nonlinear element responsible for chaotic signal generation. More importantly, the circuit parameters must be finely tuned to match the analog nonlinear dynamics of the BFO memristor with the RC network and ensure stable chaotic operation, ultimately yielding a fifth-order memristive oscillator. The proposed circuit exhibits rigorous chaos, as confirmed by Lyapunov exponent analysis, features a double-scroll attractor, and demonstrates a broad parameter range of chaotic behavior verified through bifurcation diagram analysis. This work represents the demonstration of chaos generation by leveraging, for the first time, the analog nonlinear dynamics in a self-rectifying memristor, establishing a direct link between device-level nonlinear dynamics and system-level chaotic behavior, and providing a technology-agnostic framework for the development of low-power, scalable chaotic circuits applicable to diverse applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"269-281"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11495342","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pseudo-Chebyshev Functions Over Finite Fields","authors":"Juliano B. Lima;Daniel Panario;José R. de Oliveira Neto","doi":"10.1109/OJCAS.2026.3687716","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3687716","url":null,"abstract":"In this paper, we introduce the notion of pseudo-Chebyshev functions over finite fields. In brief, such functions correspond to a generalization of the <inline-formula> <tex-math>$n$ </tex-math></inline-formula>-th Chebyshev polynomial, where <inline-formula> <tex-math>$n$ </tex-math></inline-formula> is not restricted to integer values, but can take on any rational value. Our approach is mainly based on concepts of trigonometry over finite fields. Besides defining the referred functions, we derive several of their properties and establish necessary and sufficient conditions for them to permute the elements of <inline-formula> <tex-math>$mathbb {F}_{q}$ </tex-math></inline-formula>. Potential applications of the proposed functions are preliminarily discussed.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"282-295"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11494833","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147828954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive-Resolution SAR ADC With Metastability-Sensing 1-bit TDC in 65-nm CMOS","authors":"Jørgen M. Sandvik;Trond Ytterdal","doi":"10.1109/OJCAS.2026.3718505","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3718505","url":null,"abstract":"We propose a metastability-sensing one-bit time-to-digital converter (TDC) for a successive-approximation (SAR) analog-to-digital converter (ADC) that detects a metastability-specific current in the comparator, gates its clock to stop the conversion cycle, and outputs partially resolved sub-resolution code. This approach improves the power efficiency by reducing the logic overhead and minimizing the TDC activation time. The SAR operates in the adaptive-resolution mode, using dual-rail asynchronous logic to track unresolved bits and a single-gate most significant bit (MSB) inversion to correct errors. A 7-bit capacitive digital-to-analog converter (CDAC) combined with an 8-bit SAR core generates 511 sub-resolution codes. Fabricated in 65 nm CMOS, the prototype achieves a peak SNDR of 50.6 dB at 40 MS/s, ENOB=8.16/8.11 at 1 MHz/20 MHz, and <inline-formula> <tex-math>$mathrm {40.9~mu W}$ </tex-math></inline-formula> total power (0.7 V digital/0.8 V analog), yielding a Walden figure-of-merit (FoM) of <inline-formula> <tex-math>$mathrm {3.7~fJ/conv.{,}step}$ </tex-math></inline-formula> in 0.004 mm2 active area. A static-current condition in the fabricated prototype’s TDC/comparator interface incurs excess analog power in the measured results; proposed circuit modifications are projected by simulation to eliminate this overhead.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"490-502"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11635930","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148781063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Power, Analog-Integrated, Current-Mode, and Fully Tunable Artificial Neural Network Classifier Architecture for Biomedical Engineering Applications","authors":"Vassilis Alimisis;Andreas Papathanasiou;Vasileios Moustakas;Anna Mylona;Christos Dimas;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2026.3665625","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3665625","url":null,"abstract":"This work presents a low-power, current-mode analog artificial neural network (ANN) classifier implemented in the TSMC 65-nm CMOS process and evaluated on two biomedical classification tasks. The architecture incorporates analog Sigmoid, Euclidean distance, min and argmin computation blocks to enable fully integrated feature correlation, weight adaptation, and decision-making. All circuits operate in the subthreshold regime with <inline-formula> <tex-math>$pm 0.3{V}$ </tex-math></inline-formula> supply rails. Post-layout simulations show a worst-case classification accuracy of 91.7% and strong robustness to Monte-Carlo mismatch and Process-Voltage-Temperature variations. Comparison with an equivalent software classifier and prior works validates the modeling and design methodology. The architecture achieves worst-case power consumption below 1311 nW, demonstrating its suitability for energy-constrained edge-AI applications in biomedical monitoring and diagnostics.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"158-172"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11495334","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The SpiNNaker2 Chip: A Many-Core Platform for Flexible and Scalable Brain-Inspired Computing","authors":"Stefan Scholze;Johannes Partzsch;Sebastian Höppner;Florian Kelber;Andreas Dixius;Marco Stolba;Sirine Arfa;Marc Berthel;Georg Ellguth;Jim Garside;Hector A. Gonzalez;Stephan Hartmann;Thomas Kiel-Hocker;Dongwei Hu;Matthias Jobst;Khaleelulla Khan Nazeer;Tim Langer;Chen Liu;Gengting Liu;Matthias Lohrmann;Mantas Mikaitis;Felix Neumärker;Amirhossein Rostami;Stefan Schiefer;Tilo Schubert;Delong Shang;Bernhard Vogginger;Yexin Yan;Steve Furber;Christian Mayr","doi":"10.1109/OJCAS.2026.3714974","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3714974","url":null,"abstract":"In deep learning, efficiency gets more and more important to compensate for the ongoing growth in model sizes and applications. Neuromorphic hardware has long been advocated as an upcoming alternative to deep networks, taking inspiration from the brain for achieving unprecedented energy efficiency. However, demonstrations of these gains only recently began to grow in complexity and real-world applicability. With SpiNNaker2, we present a chip that bridges the gap between deep networks and neuromorphic computing and allows for flexible exploration of computing approaches that combine both worlds. It features 152 processing elements equipped with an ARM M4F processor and dedicated accelerators, an extended SpiNNaker routing fabric for scalable event-based communication and a range of external interfaces for system integration, including Gbit Ethernet and an LPDDR4 memory interface. We demonstrate performance and efficiency of the SpiNNaker2 chip for neuromorphic and deep network workloads, as well as novel event-based computing approaches. For deep network workloads, the chip achieves up to 4.5 TOPS in high performance mode and up to 2.7 TOPS/W efficiency in high efficiency mode for INT8 workloads. The chip supports spiking neural networks with > 150000 neurons and > 1.8 billion synaptic events/s when simulated with a 1 ms time step. Its low baseline power of less than 250 mW allows for efficiency even under varying workload conditions, allowing to explore sparse and event-based modes of computation. All this demonstrates the chip’s capabilities as a universal hardware platform for scalable brain-inspired computing and its combinations with mainstream deep network approaches.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"465-478"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11614542","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comprehensive Survey on Canonical Signed Digit (CSD)-Based Multiplier Architectures: From Foundations to Modern Low-Power Implementations (1970–2025)","authors":"Maria Khan;Jari Nurmi","doi":"10.1109/OJCAS.2026.3702243","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3702243","url":null,"abstract":"The goal of this research is to trace the evolution and development of multiplier-less architectures, utilizing the Canonical Signed Digit representation from the 1970s to modern implementations through 2025. This paper examines key advances in hardware optimization that aim to reduce computational complexity, power consumption, and area usage. This paper covers the use of the CSD in diverse applications such as digital filters, image coding, and neural network accelerators. Recent advances in the use of the CSD for achieving multiplier-less architectures are highlighted, and research gaps and future work directions are discussed. The main focus is on the role of CSD in enabling efficient low-power arithmetic in real-time embedded systems and AI applications, and its relevance in emerging technologies.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"378-395"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11558359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.0 V, 5.36-μW Single-Lead ECG SoC With Chopper-Stabilized AFE, Event-Driven OvA LSVM, and PACER On-Chip False-Alarm Suppression","authors":"Muhammad Arham Sohail;Baley Heyntsen;Sohail Safdar;Simon Foo;Muhammad Awais Bin Altaf","doi":"10.1109/OJCAS.2026.3707506","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3707506","url":null,"abstract":"This paper presents a single-lead, ultra-low-power ECG system-on-chip (SoC) for real-time acquisition and multi-class arrhythmia detection at 1.0 V. The SoC integrates a chopper-stabilized analog front end (AFE), an 11-bit Successive Approximation Register Analog-to-Digital Converter sampling at 7.812 kS/s (synchronized to the gain amplifier’s mid-interval sampling), hardware feature extraction, an event-driven one-vs-all (OvA) linear support vector machine (LSVM) classifier, and an on-chip patient-adaptive false-alarm suppression block (PACER). Robust acquisition is achieved by preserving 0.1–50 Hz ECG content in the analog path and applying a light 0.5–45 Hz digital band-limiting before feature extraction. A compact five-feature vector (R-wave, S-wave, T-wave, R–R interval, Q–S interval) enables a shared-multiply-accumulate OvA LSVM implementation with minimal area/energy. Fabricated in <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS, the SoC demonstrates <inline-formula> <tex-math>$0.418~mu $ </tex-math></inline-formula>J per classification with 1–2 ms compute latency and 96.2% system-level alarm-event accuracy under inter-patient (patient-level) evaluation on MIT-BIH and Creighton University Ventricular Tachyarrhythmia datasets and achieves > 99% alarm-event-level false-alarm reduction through an on-chip severity-based PACER block. The complete chip measures 1.2 mm <inline-formula> <tex-math>$times 0.6$ </tex-math></inline-formula> mm and sustains <inline-formula> <tex-math>$5.36~mu $ </tex-math></inline-formula>W steady-state monitoring power at 1.0 V, illustrating an algorithms-in-hardware approach to clinically relevant, long-term wearable ECG monitoring.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"404-417"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11579362","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gain Modulation Using Shunting Inhibition in a Biased Subthreshold CMOS Dendrite","authors":"Luke Parker;Suma George Cardwell;Frances S. Chance;Scott Koziol","doi":"10.1109/OJCAS.2026.3667082","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3667082","url":null,"abstract":"The study of computational properties in biological nervous systems serves two important purposes: it examines the physical mechanisms underlying biological computation while also providing new models that can be utilized in bio-inspired artificial systems. We analyze a dendrite circuit designed to model and implement shunting inhibition, a mechanism in which the dominant effect is a change in transmembrane conductance that produces multiplicative or divisive effects in the membrane potential’s response when integrating synaptic inputs. Building upon our previous work, this analysis focuses on the subthreshold-linear operating region of the dendrite circuit while also showing the effects of circuit biasing, which introduces the ability for approximating linear equations with an intercept term rather than performing multiplication alone. The real-time interaction between shunting conductance and biologically realistic current input is also studied, demonstrating the multiplicative effect of shunting inhibition using time-varying inputs of different modalities. The dendrite circuit is implemented on an analog VLSI platform and uses subthreshold transistors to emulate the electrical properties of membrane channels. This implementation serves as an analog computational unit for neuromorphic system design, exemplifying how biophysical mechanisms in dendrites can inform analog neuromorphic computation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"144-157"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11406154","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}