IEEE open journal of circuits and systems最新文献_第4页

A Computer Vision-Based Framework for Snow Removal Operation Routing 基于计算机视觉的除雪作业路由框架

IEEE open journal of circuits and systems Pub Date : 2024-04-16 DOI: 10.1109/OJCAS.2023.3326274

Mohamed Karaa;Hakim Ghazzai;Yehia Massoud;Lokman Sboui

{"title":"A Computer Vision-Based Framework for Snow Removal Operation Routing","authors":"Mohamed Karaa;Hakim Ghazzai;Yehia Massoud;Lokman Sboui","doi":"10.1109/OJCAS.2023.3326274","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3326274","url":null,"abstract":"During snowfall, the utility of the road infrastructure is critical. Roads must be effectively cleared to ensure access to important locations and services. In this paper, we present an end-to-end framework for snow removal vehicle routing based on road priority. We offer an artificial intelligence-based image-based approach for estimating snow depth and traffic volume on roads. For segments monitored by CCTV cameras, we exploit images and supervised learning models to perform this task. For unmonitored roads, we use the Graph Convolutional Network architecture to predict parameters in a semi-supervised manner. Following that, we assign priority weights to all graph edges as a function of image-based attributes and road categories. We test the method using a real-world example, simulating snow removal within a study area in Montreal, Quebec, Canada. As input for the framework, we collect CCTV image data and combine it with a 2D map. As a result, more efficient snow removal operation can be achieved by optimizing the trajectories of trucks based on the computer vision module outputs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"81-91"},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500496","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier 具有均值误差最小化近似符号乘法器的低功耗 DNN 加速器

IEEE open journal of circuits and systems Pub Date : 2024-04-16 DOI: 10.1109/OJCAS.2023.3279251

Laimin Du;Leibin Ni;Xiong Liu;Guanqi Peng;Kai Li;Wei Mao;Hao Yu

{"title":"A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier","authors":"Laimin Du;Leibin Ni;Xiong Liu;Guanqi Peng;Kai Li;Wei Mao;Hao Yu","doi":"10.1109/OJCAS.2023.3279251","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3279251","url":null,"abstract":"Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency \u0000<inline-formula> <tex-math>$1.96times $ </tex-math></inline-formula>\u0000, while the error loss was only 0.95%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"57-68"},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500495","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique 利用底板开关电容器技术设计和分析容错增益增强型 N 路径接收器

IEEE open journal of circuits and systems Pub Date : 2024-04-16 DOI: 10.1109/OJCAS.2023.3335116

Yi Mao;Gengzhen Qi;Pui-In Mak

{"title":"Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique","authors":"Yi Mao;Gengzhen Qi;Pui-In Mak","doi":"10.1109/OJCAS.2023.3335116","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3335116","url":null,"abstract":"This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"92-101"},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500899","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning 利用噪声感知多目标深度学习实现硬件高效语音增强

IEEE open journal of circuits and systems Pub Date : 2024-04-16 DOI: 10.1109/OJCAS.2024.3389100

Salinna Abdullah;Majid Zamani;Andreas Demosthenous

{"title":"Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning","authors":"Salinna Abdullah;Majid Zamani;Andreas Demosthenous","doi":"10.1109/OJCAS.2024.3389100","DOIUrl":"10.1109/OJCAS.2024.3389100","url":null,"abstract":"This paper describes a supervised speech enhancement (SE) method utilising a noise-aware four-layer deep neural network and training target switching. For optimal speech denoising, the SE system, trained with multiple-target joint learning, switches between mapping-based, masking-based, or complementary processing, depending on the level of noise contamination detected. Optimisation techniques, including ternary quantisation, structural pruning, efficient sparse matrix representation and cost-effective approximations for complex computations, were implemented to reduce area, memory, and power requirements. Up to 19.1x compression was obtained, and all weights could be stored on the on-chip memory. When processing NOISEX-92 noises, the system achieved an average short-time objective intelligibility (STOI) and perceptual evaluation of speech quality (PESQ) scores of 0.81 and 1.62, respectively, outperforming SE algorithms trained with only a single learning target. The proposed SE processor was implemented on a field programmable gate array (FPGA) for proof of concept. Mapping the design on a 65-nm CMOS process led to a chip core area of \u0000<inline-formula> <tex-math>$3.88~mm^{2}$ </tex-math></inline-formula>\u0000 and a power consumption of 1.91 mW when operating at a 10 MHz clock frequency.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"141-152"},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500889","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140608718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Special Issue on Selected Papers From APCCAS 2022 2022 年亚太文化与艺术中心论文选特刊

IEEE open journal of circuits and systems Pub Date : 2024-04-15 DOI: 10.1109/OJCAS.2024.3358106

Yan Liu;Yuan Du;Yang Zhao

引用次数: 0

Computation of Graph Fourier Transform Centrality Using Graph Filter 利用图形过滤器计算图形傅立叶变换中心性

IEEE open journal of circuits and systems Pub Date : 2024-04-15 DOI: 10.1109/OJCAS.2023.3317944

Chien-Cheng Tseng;Su-Ling Lee

{"title":"Computation of Graph Fourier Transform Centrality Using Graph Filter","authors":"Chien-Cheng Tseng;Su-Ling Lee","doi":"10.1109/OJCAS.2023.3317944","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3317944","url":null,"abstract":"In this paper, the computation of graph Fourier transform centrality (GFTC) of complex network using graph filter is presented. For conventional computation method, it needs to use the non-sparse transform matrix of graph Fourier transform (GFT) to compute GFTC scores. To reduce the computational complexity of GFTC, a linear algebra method based on Frobenius norm of error matrix is applied to convert the spectral-domain GFTC computation task to vertex-domain one such that GFTC can be computed by using polynomial graph filtering method. There are two kinds of designs of graph filters to be studied. One is the graph-aware method; the other is the graph-unaware method. The computational complexity comparison and experimental results show that the proposed graph filter method is more computationally efficient than conventional GFT method because the sparsity of Laplacian matrix is used in the implementation structure. Finally, the centrality computations of social network, metro network and sensor network are used to demonstrate the effectiveness of the proposed GFTC computation method using graph filter.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"69-80"},"PeriodicalIF":0.0,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500497","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140555836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploiting Neural-Network Statistics for Low-Power DNN Inference 利用神经网络统计实现低功耗 DNN 推断

IEEE open journal of circuits and systems Pub Date : 2024-04-12 DOI: 10.1109/OJCAS.2024.3388210

Lennart Bamberg;Ardalan Najafi;Alberto Garcia-Ortiz

引用次数: 0

A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices 面向边缘设备的低功耗流式语音增强加速器

IEEE open journal of circuits and systems Pub Date : 2024-04-11 DOI: 10.1109/OJCAS.2024.3387849

Ci-Hao Wu;Tian-Sheuan Chang

{"title":"A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices","authors":"Ci-Hao Wu;Tian-Sheuan Chang","doi":"10.1109/OJCAS.2024.3387849","DOIUrl":"10.1109/OJCAS.2024.3387849","url":null,"abstract":"Transformer-based speech enhancement models yield impressive results. However, their heterogeneous and complex structure restricts model compression potential, resulting in greater complexity and reduced hardware efficiency. Additionally, these models are not tailored for streaming and low-power applications. Addressing these challenges, this paper proposes a low-power streaming speech enhancement accelerator through model and hardware optimization. The proposed high performance model is optimized for hardware execution with the co-design of model compression and target application, which reduces 93.9% of model size by the proposed domain-aware and streaming-aware pruning techniques. The required latency is further reduced with batch normalization-based transformers. Additionally, we employed softmax-free attention, complemented by an extra batch normalization, facilitating simpler hardware design. The tailored hardware accommodates these diverse computing patterns by breaking them down into element-wise multiplication and accumulation (MAC). This is achieved through a 1-D processing array, utilizing configurable SRAM addressing, thereby minimizing hardware complexities and simplifying zero skipping. Using the TSMC 40nm CMOS process, the final implementation requires merely 207.8K gates and 53.75KB SRAM. It consumes only 8.08 mW for real-time inference at a 62.5MHz frequency.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"128-140"},"PeriodicalIF":0.0,"publicationDate":"2024-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496994","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140587361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model 利用决策树模型模拟硬件架构的人体坠落雷达探测系统

IEEE open journal of circuits and systems Pub Date : 2024-03-30 DOI: 10.1109/OJCAS.2024.3407663

Vassilis Alimisis;Dimitrios G. Arnaoutoglou;Emmanouil Anastasios Serlis;Argyro Kamperi;Konstantinos Metaxas;George A. Kyriacou;Paul P. Sotiriadis

{"title":"A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model","authors":"Vassilis Alimisis;Dimitrios G. Arnaoutoglou;Emmanouil Anastasios Serlis;Argyro Kamperi;Konstantinos Metaxas;George A. Kyriacou;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2024.3407663","DOIUrl":"10.1109/OJCAS.2024.3407663","url":null,"abstract":"A fall-detection system was implemented utilizing a 2.45 GHz continuous wave radar along with power-efficient and fully-analog integrated classifier architectures. The Power Burst Curve and the effective acceleration were derived from the short time Fourier transform, and then processed by the analog classifier. The proposed classifier architectures are based on different approximations of the Decision tree classification model. The architectures consist of three main building blocks: sigmoid function circuit, analog multiplier and an argmax operator circuit. To assess the hardware design, a thorough analysis is performed, comparing it to commonly used analog classifiers while exploiting the extracted data. The architectures were trained using Python and were compared to software-based classifiers. The circuit designs were executed using TSMC’s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"224-242"},"PeriodicalIF":0.0,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10542293","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141196560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Wireless Power Conversion Chain With Fully On-Chip Automatic Resonance Tuning System for Biomedical Implants 用于生物医学植入物的带有片上全自动共振调谐系统的无线功率转换链

IEEE open journal of circuits and systems Pub Date : 2024-03-28 DOI: 10.1109/OJCAS.2024.3382355

Mohammad Javad Karimi;Menghe Jin;Catherine Dehollain;Alexandre Schmid

{"title":"A Wireless Power Conversion Chain With Fully On-Chip Automatic Resonance Tuning System for Biomedical Implants","authors":"Mohammad Javad Karimi;Menghe Jin;Catherine Dehollain;Alexandre Schmid","doi":"10.1109/OJCAS.2024.3382355","DOIUrl":"10.1109/OJCAS.2024.3382355","url":null,"abstract":"This paper presents a wireless power conversion system designed for biomedical implants, with integrated automatic resonance tuning. The automatic tuning mechanism improves power transfer efficiency (PTE) by finely tuning the resonant frequency of the power link and maximizing the rectified voltage. This adjustment ensures robust and reliable remote powering, even in the face of environmental changes and process variations, while also minimizing tissue exposure to power. On-chip switched array capacitors are connected in parallel with the resonant capacitor, and the system identifies the optimal switched capacitor combination for the highest rectified voltage by iterating over each of them. The proposed system is implemented and fabricated in standard 180nm CMOS technology, with a total area of 0.339 mm2, and its operation is verified. The measurement results demonstrate that this system provides tolerance up to mismatches equivalent to 75 pF capacitance variation in LC tank, ±15% LC variation in this design. The system offers a PTE enhancement from 9.1% to 30.2% in case of high LC variation, and the tuning control consumes 154.7\u0000<inline-formula> <tex-math>$mu text{W}$ </tex-math></inline-formula>\u0000 of power during resonance tuning. Moreover, the power conversion chain delivers an optimized rectified voltage along with a regulated voltage of 1.8 V.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"117-127"},"PeriodicalIF":0.0,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10481676","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140324283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0