{"title":"利用底板开关电容器技术设计和分析容错增益增强型 N 路径接收器","authors":"Yi Mao;Gengzhen Qi;Pui-In Mak","doi":"10.1109/OJCAS.2023.3335116","DOIUrl":null,"url":null,"abstract":"This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4000,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500899","citationCount":"0","resultStr":"{\"title\":\"Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique\",\"authors\":\"Yi Mao;Gengzhen Qi;Pui-In Mak\",\"doi\":\"10.1109/OJCAS.2023.3335116\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.\",\"PeriodicalId\":93442,\"journal\":{\"name\":\"IEEE open journal of circuits and systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.4000,\"publicationDate\":\"2024-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500899\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE open journal of circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10500899/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE open journal of circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10500899/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique
This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.