IEEE open journal of circuits and systems最新文献_第5页

RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training 流CNN的RFSoC调制分类：数据集生成和量化感知训练

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-12-03 DOI: 10.1109/OJCAS.2024.3509627

Andrew Maclellan;Louise H. Crockett;Robert W. Stewart

{"title":"RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training","authors":"Andrew Maclellan;Louise H. Crockett;Robert W. Stewart","doi":"10.1109/OJCAS.2024.3509627","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509627","url":null,"abstract":"This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"38-49"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772713","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications 有线应用中源退化差分对的线性分析

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-11-27 DOI: 10.1109/OJCAS.2024.3507543

Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone

引用次数: 0

A Generalized Active Voltage Balancing Circuit Implementation for Flying Capacitor 3-Level Switching-Mode DC–DC Converters 飞电容三电平开关模式 DC-DC 转换器的通用有源电压平衡电路实现方法

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-11-06 DOI: 10.1109/OJCAS.2024.3492320

Elisabetta Moisello;Samuele Fusetto;Piero Malcovati;Edoardo Bonizzoni

{"title":"A Generalized Active Voltage Balancing Circuit Implementation for Flying Capacitor 3-Level Switching-Mode DC–DC Converters","authors":"Elisabetta Moisello;Samuele Fusetto;Piero Malcovati;Edoardo Bonizzoni","doi":"10.1109/OJCAS.2024.3492320","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3492320","url":null,"abstract":"This paper presents a generalized control architecture for implementing the active balancing of the flying capacitor voltage in any kind of 3-level switching-mode DC-DC converters, independently from the desired conversion ratio or targeted output power level. The proposed strategy is based on the detection of the flying capacitor voltage through the inductor voltage, sensed at the switching node, and acts on the duty cycle of the PWM (Pulse Width Modulation) control signals in order to make the correction, implementing the voltage balancing. The circuit implementation and its operation are described in detail. Extensive simulations were performed in the SIMPLIS environment, taking as examples the cases of a 3-level buck, 3-level boost and 3-level inverting buck-boost DC-DC converter and considering different combinations of input voltage, output voltage and load current. Moreover, the proposed strategy was implemented in the control architecture of a hybrid switched-capacitor 3-level inverting buck-boost converter, fabricated in a 180-nm BCD process. The effectiveness and the versatility of the proposed active voltage balancing strategy and its circuit implementation were, therefore, verified both through simulations and experimentally.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"365-376"},"PeriodicalIF":2.4,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10745640","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142672080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation 基于数字本底线性校准的 DR 无损耗抖动技术，用于具有数字输入干扰消除功能的 SAR 辅助多级 ADC

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-10-28 DOI: 10.1109/OJCAS.2024.3486809

Lizhen Zhang;Bo Gao;Kun-Woo Park;Kent Edrian Lozada;Raymond Mabilangan;Hyeongjin Kim;Jianhui Wu;Seung-Tak Ryu

{"title":"DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation","authors":"Lizhen Zhang;Bo Gao;Kun-Woo Park;Kent Edrian Lozada;Raymond Mabilangan;Hyeongjin Kim;Jianhui Wu;Seung-Tak Ryu","doi":"10.1109/OJCAS.2024.3486809","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3486809","url":null,"abstract":"In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a \u0000<inline-formula> <tex-math>$50times $ </tex-math></inline-formula>\u0000 reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"349-364"},"PeriodicalIF":2.4,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736969","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142600215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling 带有重复使用的输入/输出接口和直流信号的小型防篡改、防回收集成电路传感器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-10-28 DOI: 10.1109/OJCAS.2024.3487072

Alexandros Dimopoulos;Mihai Sima;Stephen W. Neville

{"title":"A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling","authors":"Alexandros Dimopoulos;Mihai Sima;Stephen W. Neville","doi":"10.1109/OJCAS.2024.3487072","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3487072","url":null,"abstract":"Counterfeit electronic components are known to enter supply chains through recycling, with these already-aged components creating serious reliability risks, particularly for critical infrastructure systems. A number of recycled integrated circuit (IC) risk mitigation approaches have been proposed, but these generally lack pragmatic feasibility. This work proposes a novel real-world deployable on-chip sensor that: 1) is tamper-resistant by exploiting persistent changes caused by hot carrier injection (HCI); 2) generates a DC signal measurable by common low-cost test equipment; and 3) reuses an existing I/O interface, including existing pins; while 4) requiring a very small footprint. Combining this sensor with a random sample-based testing strategy allows for low-cost and time efficient detection of fraudulently recycled batches of ICs. Through simulation-based validation using process-accurate models of a 65 nm technology we show that employing a random sample size as small as 130 is sufficient for identifying such batches with a statistical significance level of 0.01.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"341-348"},"PeriodicalIF":2.4,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736936","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142600218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline 单元上的双 MAC：基于 22 纳米 8T-SRAM 的模拟内存加速器，用于二元/三元神经网络，具有分割字线功能

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-10-17 DOI: 10.1109/OJCAS.2024.3482469

Hiroto Tagata;Takashi Sato;Hiromitsu Awano

{"title":"Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline","authors":"Hiroto Tagata;Takashi Sato;Hiromitsu Awano","doi":"10.1109/OJCAS.2024.3482469","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3482469","url":null,"abstract":"This paper proposes a novel 8T-SRAM based computing-in-memory (CIM) accelerator for the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two input ports, simultaneously performing two binary multiply-and-accumulate (MAC) operations on left and right bitlines. This approach enables a twofold increase in throughput without significantly increasing area or power consumption, since the area overhead for doubling throughput is only two additional WL wires compared to the conventional 8T-SRAM. In addition, the proposed circuit supports binary and ternary activation input, allowing flexible adjustment of high energy efficiency and high inference accuracy depending on the application. The proposed SRAM macro consists of a \u0000<inline-formula> <tex-math>$128 times 128$ </tex-math></inline-formula>\u0000 SRAM array that outputs the MAC operation results of 96 binary/ternary inputs and \u0000<inline-formula> <tex-math>$96 times 128$ </tex-math></inline-formula>\u0000 binary weights as 1-5 bit digital values. The proposed circuit performance was evaluated by post-layout simulation with the 22-nm process layout of the overall CIM macro. The proposed circuit is capable of high-speed operation at 1 GHz. It achieves a maximum area efficiency of 3320 TOPS/mm2, which is \u0000<inline-formula> <tex-math>$3.4 times $ </tex-math></inline-formula>\u0000 higher compared to existing research with a reasonable energy efficiency of 1471 TOPS/W. The simulated inference accuracies of the proposed circuit are 96.45%/97.67% for MNIST dataset with binary/ternary MLP model, and 86.32%/88.56% for CIFAR-10 dataset with binary/ternary VGG-like CNN model.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"328-340"},"PeriodicalIF":2.4,"publicationDate":"2024-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10721281","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142579204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers 降低离散多音有线接收器峰均比的压缩技术

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-07-16 DOI: 10.1109/OJCAS.2024.3427693

Miad Laghaei;Hossein Shakiba;Ali Sheikholeslami

{"title":"A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers","authors":"Miad Laghaei;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2024.3427693","DOIUrl":"10.1109/OJCAS.2024.3427693","url":null,"abstract":"Multicarrier modulation, while providing a theoretical pathway to data rates approaching the Shannon limit and being extensively utilized in wireless communication, has encountered limited application in high-speed wireline communication. This limitation is primarily due to substantial large amplitude peaks, which necessitates a reduction in the signal’s power levels to circumvent signal clipping. This, in turn, results in a low signal-to-noise ratio (SNR) which puts these modulations at a serious disadvantage compared to conventional modulation schemes. This work proposes a novel companding solution in the design of the Continuous Time Linear Equalizer (CTLE) alongside nonlinear blocks to reduce Peak to Average Power Ratio (PAPR), therefore improving the overall link performance. This paper presents a PAPR reduction technique and its implementation in the receiver, distinguishing it from previous studies that place the compander at the transmitter where it fails to work in the presence of an Inter-Symbol Interference (ISI) channel. A theoretical study as well as an implementation of this method is provided, and the merits and performance improvements are demonstrated.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"302-313"},"PeriodicalIF":2.4,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10599803","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141719644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective 低功耗片上能量收集：从接口电路的角度看

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-07-04 DOI: 10.1109/OJCAS.2024.3423484

Shuang Song;Dehong Wang;Mengyu Li;Siyao Cao;Feijun Zheng;Kai Huang;Zhichao Tan;Sijun Du;Menglian Zhao

引用次数: 0

A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction 具有主动周期抖动校正功能的 10 GHz 双环 PLL，可实现 12dB Spur 和 29% 的抖动降低率

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-06-18 DOI: 10.1109/OJCAS.2024.3416397

Yu-Ping Huang;Yu-Sian Lu;Wei-Zen Chen

引用次数: 0

A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI 利用 22 纳米 FDSOI 6 抽头 MIMO-FFE 的 45Gb/s 模拟多音接收器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2024-06-13 DOI: 10.1109/OJCAS.2024.3414252

Jhoan Salinas;Hossein Shakiba;Ali Sheikholeslami

引用次数: 0