IEEE open journal of circuits and systems最新文献_第5页

An FPGA-Calibrated Modulo ADC for High-Dynamic-Range Signal Acquisition 用于高动态范围信号采集的fpga校准模数转换器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-03-18 DOI: 10.1109/OJCAS.2026.3694303

Zeyuan Li;Wenyi Yan;Lu Gan;Guoquan Li;Hongqing Liu

{"title":"An FPGA-Calibrated Modulo ADC for High-Dynamic-Range Signal Acquisition","authors":"Zeyuan Li;Wenyi Yan;Lu Gan;Guoquan Li;Hongqing Liu","doi":"10.1109/OJCAS.2026.3694303","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3694303","url":null,"abstract":"Conventional analog-to-digital converters (ADCs) suffer from irreversible clipping when input amplitudes exceed their fixed full-scale range. Modulo ADCs address this by folding the input signal prior to quantization; however, stable hardware operation under deep-folding conditions and experimental validation of algorithmic recoverability remain outstanding challenges. This paper presents a calibrated FPGA-based modulo ADC platform in which a finite state machine with multi-bit update control governs folding dynamics, replacing instantaneous comparator-triggered feedback to ensure deterministic and stable operation. A controlled under-compensation calibration strategy converts fold-dependent threshold mismatch and oscillatory instability into a bounded constant residual, enabling reliable folding at high folding depths. The platform achieves a dynamic range expansion exceeding two orders of magnitude while maintaining signal fidelity comparable to that of the standalone ADC. Experimental validation across diverse waveforms confirms robust signal acquisition and demonstrates the practical feasibility of dynamic-range extension using modulo sampling principles.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"296-307"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11523046","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a Hybrid Asymmetric LMBA With High Linearity Based on Improved Particle Swarm Optimization Method 基于改进粒子群优化方法的高线性混合非对称LMBA设计

IF 1.8

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-03-26 DOI: 10.1109/OJCAS.2026.3678037

Benhao Jin;Zhiming Fan;Giovanni Crupi;Jialin Cai

{"title":"Design of a Hybrid Asymmetric LMBA With High Linearity Based on Improved Particle Swarm Optimization Method","authors":"Benhao Jin;Zhiming Fan;Giovanni Crupi;Jialin Cai","doi":"10.1109/OJCAS.2026.3678037","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3678037","url":null,"abstract":"This paper presents an improved particle swarm optimization (PSO) method and applies it to the design of a hybrid asymmetric load modulated balanced amplifier (H-ALMBA) with high linearity. A description is provided of the H-ALMBA topology as well as the improved PSO method with individually self-adaptive hyperparameters (Improved PSO-ISH). The design process as well as the optimization procedure are described in detail. In addition to output power and efficiency, linearity performance, including AM/AM and AM/PM characteristics, is also considered during optimization. The performance of H-ALMBA optimized by the proposed method is presented and compared to the initial design, the ADS built-in optimizer, and other methods of PSO that are currently available. Due to the introduction of Latin hypercube sampling (LHS) and a secondary optimization step in the improved PSO-ISH method, the optimization performance has been greatly enhanced. According to the measured results, the H-ALMBA designed using the proposed method achieves a saturation drain efficiency (DE) between 59.5% and 64.8%, and a DE of 45.7%-58.1% in the 10dB output back-off state (OBO), with an output power of 41.5 dBm-44.2 dBm from 1.8GHz to 2.6GHz. The variation range of AM/AM is less than 4.1dB and that of AM/PM is less than 11.5°, demonstrating high linearity. Additionally, modulated signal tests are conducted. A 20-MHz 5G new radio (NR) signal with 10-dB peak-to-average power ratios (PAPRs) is used. A high level of linearity is achieved without the use of digital predistortion (DPD).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"353-365"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11456788","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An IEEE-754 FP32 Marsaglia–Polar Gaussian RNG on FPGA With AES-CTR Uniform Feeder 基于AES-CTR均匀馈线的IEEE-754 FP32 Marsaglia-Polar高斯RNG

IF 1.8

IEEE open journal of circuits and systems Pub Date : 2026-01-01 Epub Date: 2026-07-14 DOI: 10.1109/OJCAS.2026.3713363

Arnab Kumar Biswas

{"title":"An IEEE-754 FP32 Marsaglia–Polar Gaussian RNG on FPGA With AES-CTR Uniform Feeder","authors":"Arnab Kumar Biswas","doi":"10.1109/OJCAS.2026.3713363","DOIUrl":"https://doi.org/10.1109/OJCAS.2026.3713363","url":null,"abstract":"We present a standards-compliant IEEE 754 FP32 Gaussian random number generator (GRNG) for FPGA based on the Marsaglia–polar method, designed to deliver verifiable tails and reproducible floating-point semantics for scientific and security-relevant workloads. The key contribution is a streaming, tokenized polar architecture that (i) cleanly separates the uniform feeder from the Gaussian transform core (AES–CTR by default, swappable by threat model), and (ii) uses IEEE-field-based accept–reject gating to avoid invoking expensive <inline-formula> <tex-math>${ln,div,sqrt {cdot }}$ </tex-math></inline-formula> stages on invalid samples, improving pipeline efficiency while preserving IEEE 754 behavior. We complement empirical ULP/relative-error checks with an explicit conditioning-based stability analysis of the <inline-formula> <tex-math>$ln (s)rightarrow /s rightarrow sqrt {cdot }$ </tex-math></inline-formula> chain and validate statistical fidelity via histograms, Q–Q plots, Kolmogorov–Smirnov distances, independence checks, and large-<inline-formula> <tex-math>$N$ </tex-math></inline-formula> tail stress testing. Application-level evaluations (BER-over-AWGN for BPSK and DP-style Gaussian noise injection in ML) include software baselines and confidence bounds to demonstrate system-level fidelity. On a Xilinx Artix–7, the post-route design meets 400 MHz and produces two samples per cycle (800 MS/s) using 1535 LUTs and 12 DSPs, with total power 0.264 W (dynamic 0.132 W); an ASIC-scaled projection to 22 nm provides contextual throughput comparison.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"7 ","pages":"418-433"},"PeriodicalIF":1.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11609285","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Control Method for Unbalanced Current in Grid Type Energy Storage Based on Negative Sequence Virtual Impedance 基于负序虚阻抗的电网储能不平衡电流控制方法

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-12-10 DOI: 10.1109/OJCAS.2025.3532762

Li You;Liangli Xiong;Gang Han;Sheng Zhang;Zhijian Fang

{"title":"A Control Method for Unbalanced Current in Grid Type Energy Storage Based on Negative Sequence Virtual Impedance","authors":"Li You;Liangli Xiong;Gang Han;Sheng Zhang;Zhijian Fang","doi":"10.1109/OJCAS.2025.3532762","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3532762","url":null,"abstract":"Grid type energy storage has inertia support capability, and unbalanced grid voltage will cause grid type energy storage current fluctuation and active power fluctuation. In this paper, a control method for unbalanced current in grid type energy storage based on negative sequence virtual impedance is proposed, analyze the reasons for the fluctuation of grid type energy storage current, and adopts the inner-loop positive-negative sequence separation control method, adding virtual impedance to suppress the negative sequence current only in the negative sequence control loop. And the relationship between the virtual impedance values and system stability in the background of grid harmonics are analyzed. Finally, simulations and experiments show that the addition of virtual impedance only in negative sequence does not affect the normal operating conditions, but has the characteristic of producing effects under unbalanced grid voltage. The method is simple to implement and the output current and active power fluctuations of the grid type energy storage are effectively suppressed.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"477-486"},"PeriodicalIF":2.4,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11293418","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Double-Channel Constant Voltage Output Design in Magnetically Coupled Wireless Power Transfer Systems With the Anti-Misalignment Capability 具有抗失调能力的磁耦合无线输电系统的双通道恒压输出设计

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-12-09 DOI: 10.1109/OJCAS.2025.3541626

Zhiheng Zhao;Jinhong Sun

引用次数: 0

AI-Enhanced Wide Supply Voltage Bandgap Voltage Reference Circuit With Multi-Objective Optimization for Automotive Applications 汽车应用的多目标优化ai增强型宽电源带隙电压参考电路

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-12-09 DOI: 10.1109/OJCAS.2025.3531412

U Chi-Wa;Zhaoxi Li;Cheng-Hou Cheong;Chon-Fai Lee;Chi-Seng Lam

引用次数: 0

Learning-Based Predictive Virtual Inertia Control for Frequency Regulation in Low Inertia Power Grids 基于学习的低惯量电网频率预测虚拟惯量控制

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-12-09 DOI: 10.1109/OJCAS.2025.3535919

Osarodion Emmanuel Egbomwan;Shichao Liu;Hicham Chaoui;Xiaozhe Wang

{"title":"Learning-Based Predictive Virtual Inertia Control for Frequency Regulation in Low Inertia Power Grids","authors":"Osarodion Emmanuel Egbomwan;Shichao Liu;Hicham Chaoui;Xiaozhe Wang","doi":"10.1109/OJCAS.2025.3535919","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3535919","url":null,"abstract":"The increasing integration of renewable energy generators into the conventional power grid has lowered the overall power system inertia. Low inertia may adversely impact the grid’s stability and resilience, leading to unintended grid failure and total system collapse upon severe contingencies. Current methods of emulating power grid inertia to enhance stability under low inertia conditions have some drawbacks. For example, the proportional-integral (PI) control method suffers from high overshoot and settling time, while the performance of the conventional model predictive controller (MPC) is highly dependent on the accuracy of the system model. Consequently, a new learning-based predictive virtual inertia control (VIC) is proposed. This strategy incorporates a physics-informed neural network (PINN) predictive model with an optimization-based safety filter to mitigate the impact of increasing integration of renewable energy generators through a virtual inertia emulation strategy. Our proposed strategy leverages advances in deep learning by implementing a PINN-based model to predict the system’s future behavior. The proposed method is compared to the MPC and PI controller. The results demonstrate the superior dynamic performance of the proposed method. Our implemented technique achieved the least frequency deviations upon contingencies in the IEEE 34 bus and the IEEE 39 bus studied systems with integrated inverter-based generators.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"504-519"},"PeriodicalIF":2.4,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11286041","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 30-70MHz Delay-Line-Based Multiphase 50A 5.14 A/mm² Fully Integrated Voltage Regulator 一种30-70MHz基于延迟线的多相50A 5.14 A/mm²全集成稳压器

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-12-02 DOI: 10.1109/OJCAS.2025.3639222

Tianshu Liu;Tao Zhang;Yukan Du;Wanyuan Qu

{"title":"A 30-70MHz Delay-Line-Based Multiphase 50A 5.14 A/mm² Fully Integrated Voltage Regulator","authors":"Tianshu Liu;Tao Zhang;Yukan Du;Wanyuan Qu","doi":"10.1109/OJCAS.2025.3639222","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3639222","url":null,"abstract":"This paper introduces a fully integrated 4-phase 16-channel Buck converter capable of delivering up to 50A of current with a vertical power delivery structure. The converter employs a delay-line-based pulse-width modulation scheme, which ensures decent duty cycle matching across all phases. To further enhance performance, an accurate high-speed full-wave current sensor and a current-balance feedback loop are incorporated to actively regulate and balance current distribution among all 16 channels. Furthermore, substrate metals are adopted to implement the vertical 3D air-core inductors to verify the proposed vertical power delivery. Fabricated in 28nm CMOS technology, the prototype achieves a peak efficiency of 87% and supports a maximum load current of 50A, with an impressive die-area current density of 5.14A/mm2. Under a 50MHz switching frequency, the converter exhibits a measured bandwidth of 7.1MHz and a phase margin of 55°, demonstrating robust stability. The worst-case average current imbalance across all phases is limited to 10.7% over the full load range. These results indicate that the proposed design is highly suitable for high-density power management in advanced multi-core System-on-Chips (SoCs).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"520-529"},"PeriodicalIF":2.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11271853","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High Throughput Arithmetic Computing Unit for BFV Homomorphic Encryption BFV同态加密的高吞吐量算术计算单元

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-11-25 DOI: 10.1109/OJCAS.2025.3581188

Rella Mareta;Ardianto Satriawan;Hanho Lee

引用次数: 0

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI MARVEL：为轻量级AI生成模型类感知自定义RISC-V扩展的端到端框架

IF 2.4

IEEE open journal of circuits and systems Pub Date : 2025-11-25 DOI: 10.1109/OJCAS.2025.3589132

M. Ajay Kumar;Cian O’Mahoney;Pedro Kreutz Werle;Shreejith Shanker;Dimitrios S. Nikolopoulos;Bo Ji;Hans Vandierendonck;Deepu John

{"title":"MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI","authors":"M. Ajay Kumar;Cian O’Mahoney;Pedro Kreutz Werle;Shreejith Shanker;Dimitrios S. Nikolopoulos;Bo Ji;Hans Vandierendonck;Deepu John","doi":"10.1109/OJCAS.2025.3589132","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3589132","url":null,"abstract":"Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD’s FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL–an automated, end-to-end framework that generates custom RISC-V ISA extensions tailored to specific DNN model classes, with a primary focus on convolutional neural networks (CNNs). The proposed method profiles high-level DNN representations in Python and generates an ISA-extended RISC-V core with associated compiler tools for efficient deployment. The flow leverages (1) Apache TVM for translating high-level Python-based DNN models into optimized C code, (2) Synopsys ASIP Designer for identifying compute-intensive kernels, modeling, and generating a custom RISC-V and (3) Xilinx Vivado for FPGA implementation. Beyond a model-class specific RISC-V, our approach produces an optimized bare-metal C implementation, eliminating the need for an OS or extensive software dependencies. Unlike conventional deployment pipelines relying on TensorFlow/PyTorch runtimes, our solution enables seamless execution in highly resource-constrained environments. We evaluated the flow on popular DNN models such as LeNet-5*, MobileNetV1, ResNet50, VGG16, MobileNetV2 and DenseNet121 using the Synopsys trv32p3 RISC-V core as a baseline. Results show a <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> speedup in inference and upto <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> reduction in energy per inference at a 28.23% area overhead when implemented on an AMD Zynq UltraScale+ ZCU104 FPGA platform.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"445-456"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0