A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC

This paper provides a critical review and the classification of comparators in low-power low-data-rate (1 kS/s~1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs). Both voltage-domain and time-domain comparators are studied and their pros and cons are examined. The architecture, comparison time, and power consumption of five widely used voltage-domain dynamic comparators are studied first. It is followed with an investigation of kickback in comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converters (DACs) of SAR ADCs arising from the different resistances of DAC switches gives rise to a differential clock kickback that occurs earlier than output kickback with more strength hence dictating kickback in dynamic comparators. If the strength and duration of clock kickback are sufficiently large, the comparator will yield an erroneous output. The dependence of clock kickback on the input of SAR ADCs in the least significant bit (LSB) conversion is also investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are investigated, and the minimum tuning bits of digitally tuned offset compensation capacitor arrays is obtained. The noise of dynamic comparators is also investigated and design trade-offs between noise, power consumption, kickback, and the loading of the comparator on DAC are examined. The extensive simulation results of the comparators designed in a TSMC 130 nm 1.2 V CMOS technologies with reduced supply voltages and analyzed using Spectre from Cadence Design Systems with BSIM 3.3 device models are provided.