Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC

Abstract

This paper presents a sub-threshold all-digital delay-locked loop (DLL) for the generation of the timing signals of low-power low-data-rate successive approximation register analog-to-digital converters. The delay line of the DLL consists of a set of cascaded static inverters with its large per-stage-delay obtained by powering the delay with an exceedingly low supply voltage. The per-stage-delay of the delay line is adjusted by varying the supply voltage provided by a sub-threshold voltage generator. Voltage recovery blocks consisting of cascaded static inverters with different supply voltages are used to recover the low voltage swing of the delay line to the nominal voltage swing of the DLL. High-voltage-threshold pMOS transistors are used to minimize the short-circuit-induced power consumption of voltage-recovering inverters. The proposed DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3v3 device models. Simulation results show the DLL locks to a $0\sim 0.6$ V 100 kHz 50% duty cycle external timing reference at FF/0.6V/- $20^{o}$ C, TT/0.6V/ $27^{o}$ C, and SS/0.6V/ $60^{o}$ C in approximately 7 cycles of the timing reference with no accumulated static phase errors. The DLL occupies an area of 0.00559 mm2, offers 0.35% normalized root-mean-square jitter, and consumes 92 nW.