利用分数分频器的高线性度超宽带参考频率啁啾发生器

IF 2.4 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Bent Walther;Lukas Polzin;Marcel van Delden;Thomas Musch
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引用次数: 0

摘要

基于线性频率啁啾的毫米波测量系统使用物理分离的多输入多输出(MIMO)系统,对生成调制参考啁啾以应用高相干性提出了独特的挑战。参考频率啁啾对整个系统的测量精度至关重要,应具有高带宽、低相位噪声和高线性度的特点。为此,我们提出了一种新颖的架构,将固定整数锁相环(PLL)与快速调制分频器相结合。因此,可实现高达 2 GHz 的调制输出频率和高达 1.75 GHz 的可调带宽,同时与中心频率的载波保持 -140 dBc/Hz 的低相位噪声。小数分频器的同步编程和调制是通过现场可编程门阵列(FPGA)中的新型快速收发器控制完成的,无需对分频器进行反向同步。利用新型参考频率啁啾发生器和 V 波段 PLL 进行的测量显示,在啁啾持续时间为 1 毫秒、带宽为 363 兆赫的情况下,参考啁啾的均方根线性误差仅为 0.67ppm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Ultra-Wideband Reference Frequency Chirp Generator Utilizing Fractional Frequency Divider With High Linearity
Using physically separated multiple-input multiple-output (MIMO) systems for millimeter-wave measurement systems based on linear frequency chirps poses unique challenges for generating a modulated reference chirp to apply high coherence. The reference frequency chirp is crucial for the measurement accuracy of the overall system and should feature high bandwidth, low phase noise, and high linearity. For this reason, we present a novel architecture combining a fixed-integer phase-locked loop (PLL) with a fast-modulated frequency divider. Thus, modulated output frequencies of up to 2 GHz with an adjustable bandwidth of up to 1.75 GHz are achieved while maintaining low phase noise of −140 dBc/Hz at 1 MHz from the carrier at the center frequency. Synchronous programming and modulation of the fractional frequency divider is done by a new type of control utilizing fast transceivers in a field-programmable gate array (FPGA), which does not require back-synchronization to the frequency divider. Measurements with the novel reference frequency chirp generator combined with a V-band PLL reveal a low RMS linearity error of 0.67ppm of the reference chirp for a chirp duration of 1 ms and a bandwidth of 363 MHz.
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