IEEE open journal of power electronics最新文献

{"title":"Weighting-Factor-Free Sequential Predictive Torque Control Using Virtual Vectors in Six-Phase IM","authors":"Paola Maidana;Christian Medina;Jesús Doval-Gandoy;Jorge Rodas;Osvaldo Gonzalez;Magno Ayala;Raul Gregor","doi":"10.1109/OJPEL.2026.3719597","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3719597","url":null,"abstract":"Finite-control-set model predictive torque control of multiphase induction machines is often limited by heuristic tuning of weighting factors and inadequate secondary-plane current regulation. To address these limitations, this paper proposes a weighting-factor-free sequential model predictive torque control strategy with virtual voltage vector synthesis (SMPTC-VV) for six-phase induction machine drives supplied by dual two-level voltage source inverters. The proposed scheme employs a sequential optimisation structure that removes weighting factors from the cost function formulation. Virtual voltage vectors are incorporated to suppress non-torque-producing currents in the <inline-formula><tex-math>$x-y$</tex-math></inline-formula> plane, enabling simultaneous regulation of electromagnetic torque, stator flux, and secondary-plane currents. Experimental validation under steady-state and dynamic conditions, including <inline-formula><tex-math>$pm$</tex-math></inline-formula>25% magnetising inductance mismatch, demonstrates accurate torque and flux regulation, fast transient response, and improved current quality. The proposed strategy achieves improvements of 10.08% and 53.41% in <inline-formula><tex-math>$text{THD}_alpha$</tex-math></inline-formula>, and 54.26% and 69.21% in <inline-formula><tex-math>$text{THD}_{a}$</tex-math></inline-formula>, compared to SMPTC and classical PTC, respectively. In addition, flux regulation is improved by 28.03% and 31.13% relative to SMPTC and classical PTC, respectively, while non-torque-producing <inline-formula><tex-math>$x-y$</tex-math></inline-formula> currents are improved by 75.40% and 82.58% with respect to SMPTC and classical PTC. The computational effort is limited to 966 floating-point operations per sampling period, corresponding to improvements of 50.66% and 75.66% relative to SMPTC and classical PTC, respectively. The results demonstrate an efficient and experimentally validated predictive torque control solution for high-performance multiphase drives.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"2288-2300"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11641751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Online Milliohm Variation Detector for Assessing Battery Internal Resistance","authors":"Sebastian Maldonado;Emilio López;Luis Ibarra;Renato Galluzzi;Jesús Camacho;Alberto Ponso;Angelo Bonfitto","doi":"10.1109/OJPEL.2026.3682658","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3682658","url":null,"abstract":"This work introduces an online technique to detect variations at the milliohm-level of the equivalent internal resistance in a battery. This method is based on the voltage ripple generated by a DC-DC switching converter operating normally as its charger. It targets simple battery-associated hardware that measures only terminal voltage and output current, without additional excitation signals or specialized impedance instrumentation. An online dynamical model of the nominal converter–battery system replicates the baseline terminal voltage ripple generated under the same PWM input. The online-calculated covariance matrix for the measured and model-predicted ripple components is used to reveal variations in the internal resistance. Experimental validation, using a lead-acid battery together with a series-connected resistor network in the m<inline-formula><tex-math>$Omega$</tex-math></inline-formula> range to emulate an increase in internal resistance, showed smooth, monotonic dependencies between the proposed descriptors and resistance variations. This proof of concept suggests that converter-induced switching ripple could potentially support state-of-health estimation based on internal-resistance variations, using lightweight statistics compatible with typical charging hardware.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1256-1264"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11478625","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147736959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive Power–Time Coupled Synchronization for DC-Bus Ripple Suppression in Single-Phase AC–DC–AC Voltage Regulators","authors":"Da Xie;Miao Huang;Jinkun Li","doi":"10.1109/OJPEL.2026.3692139","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3692139","url":null,"abstract":"The inherent second-order power oscillation of the single-phase AC-DC-AC voltage regulator under wide input voltage conditions will cause significant ripple in the DC bus voltage, especially when the load changes suddenly. The traditional synchronous method based on phase-locked loop (PLL) only focuses on phase tracking and does not consider the direct impact of the synchronous timing on the DC bus ripple. This paper reveals that the timing mismatch between the grid voltage and the zero-crossing point of the inverter output voltage is the key factor determining the amplitude of the DC bus ripple, clarifies the intrinsic mechanism of power-time coupling, and establishes the analytical relationship between second-order power mismatch, timing deviation and bus ripple. Based on this, a power-time coupling adaptive synchronization method is proposed, which takes the synchronization timing as a controllable variable, extracts the second-order voltage ripple of the DC bus and introduces a slow adaptive compensation loop. The timing deviation at the zero-crossing point is adjusted without changing the internal structure of the PLL. Through the experimental prototype of the single-phase AC-DC-AC voltage regulator, it is verified that the proposed method can effectively suppress the DC bus voltage ripple under wide input voltage and dynamic load switching. Compared with the traditional PLL synchronization and fixed timing compensation methods, it has better steady-state and transient performance, and maintains a stable output voltage, demonstrating engineering practicability.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1672-1687"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11515138","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Synthesis of Fully Soft-Switching Flying-Capacitor-Based Quasi-Resonant DC–DC Converters","authors":"Kumar Joy Nag;Aleksandar Prodić","doi":"10.1109/OJPEL.2026.3684892","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3684892","url":null,"abstract":"This article presents a generalized design methodology for a recently introduced class of soft-switching, flying-capacitor-based quasi-resonant (FC-QR) converters. This class achieves soft-switching across all transition edges, independent of the load and voltage conversion ratio (VCR) – highly desirable features for high-VCR and low-power supplies, where switching losses are dominant. Operating-condition-independent soft-switching is achieved by operating the flying capacitor (FC) in discontinuous voltage mode (DVM), i.e., allowing it a full voltage swing. At the same time, the inductor is operated in discontinuous conduction mode (DCM). This DVM–DCM operation is obtained through a specifically developed control scheme. These topologies achieve practically flat and high-efficiency curves that only drop slightly at very light loads. The foundation for the converter and controller synthesis and analysis is based on a developed set of generic assumptions (applicable for all dc–dc converters) and guidelines, covering the design of step-up/step-down, isolated/non-isolated, and single/multi-resonant topologies, as well as their complementary controllers. Consequently, the developed framework provides useful tools for the complete design and analysis of the entire class of FC-QR-based power supplies. Based on the developed guidelines, as a practical design example, an FC-QR boost converter is developed. The experimental prototype demonstrates class-leading peak efficiency of 88% for a 2–5 V input and a 30–60 V / 3 W output, in a small form factor, confirming the effectiveness of the introduced generalized synthesis and analysis framework.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1309-1328"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11482813","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fast-Transient PLL-Assisted COT Buck Converter With Valley-Clamped Ramp Compensation for High Accuracy","authors":"Pang-Jung Liu;Pei-Xuan Ding","doi":"10.1109/OJPEL.2026.3686903","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3686903","url":null,"abstract":"This paper presents a 0.35-μm CMOS buck converter with valley-clamped internal ramp compensation for ripple-based constant on-time (COT) control. The proposed technique enables stable operation with low-ESR output capacitors while suppressing the DC output offset introduced by conventional compensation methods. To mitigate the transient-response degradation caused by ramp compensation, a transient enhancement circuit is employed to accelerate output-voltage recovery. In addition, a phase-locked loop (PLL) is incorporated to achieve pseudo-fixed-frequency operation in continuous conduction mode (CCM). Experimental results show that the output DC offset is below 3 mV over a load range of 50 mA to 1000 mA. For a 700-mA load step, the recovery times are 1.3 μs and 1.2 μs for step-down and step-up transitions, respectively. Moreover, the switching frequency is regulated at approximately 1 MHz with less than 0.7% variation under load changes from 300 mA to 1000 mA. The prototype achieves FOM₁ values of 5.38/5.83 and FOM₂ values of 17.95/19.44 for step-down/step-up operation, demonstrating competitive transient performance and DC accuracy compared with reported switching on-time controlled CMOS buck converters.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1440-1452"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11493922","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147828904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analytical Switching Loss Model for GaN Gate Injection Transistors","authors":"Ruida Zhang;Jürgen Biela","doi":"10.1109/OJPEL.2026.3687420","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3687420","url":null,"abstract":"Gallium nitride (GaN) high electron mobility transistors (HEMTs) are increasingly adopted in highly efficient power converters. In the design and optimization of GaN-based converters, accurate analytical models with low computational effort are required for predicting the switching losses. This paper proposes a novel equivalent-circuit-based switching loss model for GaN gate injection transistors (GITs). Due to the inserted p-GaN layer and the ohmic-contact gate structure, the gate capacitance of GaN GITs depends on the gate-voltage bias, and a specialized gate drive circuit is required to maintain a leakage gate current during conduction, both of which are incorporated in the proposed model. While most conventional loss models rely on curve fitting and numerical solvers, making them device-specific and prone to convergence issues, the proposed model avoids these shortcomings by using piecewise linearization and thus achieves higher generality and reliability. The switching waveforms predicted by the proposed model match closely with the experimental measurements, with average switching loss errors below 15% for both turn-on and turn-off over a wide operating range.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1426-1439"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11494270","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147828905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite Control Set Model Predictive Control for Current Ripple Reduction on BLDC Motors","authors":"Axel Coronado-Andrade;Luis Alvarez-Icaza","doi":"10.1109/OJPEL.2026.3694702","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3694702","url":null,"abstract":"Two new techniques are presented for finite control set model predictive control (FCS-MPC) of BLDC motors in high performance applications. The proposals are based on two design choices: a) a reduced set of admissible switching states, selected according to the electrical sector in which the motor is functioning, and b) the division of the sampling time into a fixed number of sub-intervals. These two choices, together with a proper formulation for the prediction of current values, allow to easily calculate the value of a predefined cost function at the end of the sampling time, for all possible combinations of admissible switchings during the sub-intervals, and to select the one that minimizes this cost function. The chosen combination is then applied using a standard voltage source inverter (VSI). These two techniques do not require the calculation of any switching time and keep the simplicity of the original FCS-MPC scheme. Simulation and experimental results, under similar conditions, show superior performance with a reduction between 70% to 80% of the RMSE current tracking error, when compared with the original FCS-MPC. These new techniques are complementary to control strategies that deal with load and speed variations in BLDC motors desired trajectories.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1753-1766"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11524065","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantitative Reliability Design Framework for Pressureless Sintered Silver Joints Based on Accumulated Plastic Strain","authors":"Keisuke Wakamoto;Ayumi Saito;Ken Nakahara","doi":"10.1109/OJPEL.2026.3724922","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3724922","url":null,"abstract":"This paper proposes a quantitative reliability design framework for pressureless sintered silver (PL-s-Ag) die-attach layers by characterizing their degradation under four levels of cyclic bending forces. The PL-s-Ag layer was bonded to a Ti-6Al-4V alloy substrate with a sputtered Ag surface at 300 °C for 10 min under 0.7 MPa. A nine-point bending test (NBT) was implemented to produce concentric principal tensile stress at 150 °C. Weibull plots of the degradation ratio (DR) after 50k NBT cycles, the ratio of degraded area to the total area via scanning acoustic tomography, exhibit linear trends despite their complex degradation morphology. The plots also reveal that a larger applied force level leads to a larger characteristic scale parameter (η) and a smaller shape parameter (m). This failure mode shift is further confirmed by multi-scale scanning electron microscopy (SEM) observations, transitioning from localized surface grain openings to an internal pore coalescence coupled with interfacial cracking. Finite element analysis (FEA) was performed to characterize the spatial distribution of the accumulated plastic strain (APS) per cycle, denoted as APSpc. The spatial distributions of APSpc are consistent with the morphological observations by SEM. The DR correlates with the APSpc averaged over the FEA analysis areas via a power-law relationship, indicating that the APSpc super-linearly increases the variation in the DR, thereby narrowing the reliable design window. Consequently, maintaining the mean APSpc below 1.5 × 10⁻³ is essential for ensuring the robust reliability of PL-s-Ag die-attach materials. (Note that the organization of the body of the paper is at the authors’ discretion; the only required sections are Introduction, Methods and Procedures, Results, Conclusion, and References. Acknowledgements and Appendices are encouraged but optional.)","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"2498-2510"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11658621","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Dual T-Type Self-Balanced Modular N-Level Inverter With Reduced Switch Count","authors":"Salvatore Foti;Gabriele Ruggeri;Tommaso Scimone;Gioele Baia;Antonio Testa;Salvatore De Caro","doi":"10.1109/OJPEL.2026.3705086","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3705086","url":null,"abstract":"This paper introduces a new modular N-level inverter topology that reduces the number of active devices and the cost compared to conventional multilevel inverter topologies, such as Neutral Point Clamped, Flying Capacitor, T-Type and- Cascaded H-Bridge. The proposed topology produces an N-level output and inherently ensures capacitor voltage self-balancing, thereby eliminating the need for auxiliary sensors or voltage-balancing algorithms while reducing cost and power losses. A nearest-level modulation strategy is employed to enhance flexibility and facilitate digital implementation, particularly in high-level converters, by directly computing the switching states and duty cycles for each phase without the use of a triangular carrier wave. Experimental validation on a 1.5-kW prototype confirms the effectiveness of the proposed topology in terms of efficiency and power quality. Furthermore, the proposed configuration has been benchmarked against existing topologies with respect to total standing voltage, component count, power quality, and cost function.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1911-1928"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11570059","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Unified Digital State-Feedback Control Strategy With Explicit Decoupling for a Hybrid Multiport DC–AC Converter in Standalone PV-HESS Applications","authors":"Diego Rojas;Duberney Murillo-Yarce;Abraham López;Javier Muñoz;Patricio Gaisse","doi":"10.1109/OJPEL.2026.3714813","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3714813","url":null,"abstract":"This paper presents a hybrid multiport DC–AC conversion system for standalone AC power supply, consisting of a multiport DC–DC stage cascaded with a single-phase voltage-source inverter (VSI). The multiport DC–DC stage interfaces a photovoltaic (PV) module, a battery bank, and a supercapacitor bank, while the VSI directly supplies off-grid AC loads. Unlike conventional approaches that employ separate controllers for the DC–DC and DC–AC stages, this work proposes a unified digital state-feedback control strategy with explicit decoupling networks. This framework enables fully independent and simultaneous regulation of all four ports (PV voltage, battery current, supercapacitor current, and AC output voltage) while effectively mitigating the strong cross-coupling among the DC ports and between the DC–DC and DC–AC stages. The proposed controller is supported by a comprehensive small-signal model of the hybrid system and is validated through PSIM simulations and experimental results from a laboratory prototype. The results demonstrate fast inner-loop dynamics, negligible cross-coupling under reference changes, and robust operation across multiple power-flow modes.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"2091-2111"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11614460","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}