IEEE open journal of power electronics最新文献

{"title":"Distributed Controller for the Parallel Operation of Power Converters With Small Output Filters","authors":"Matteo Dalboni;Alessandro Soldati","doi":"10.1109/OJPEL.2024.3437637","DOIUrl":"10.1109/OJPEL.2024.3437637","url":null,"abstract":"This study addresses the design of a distributed controller, mostly intended for modular applications where parallel-connected voltage-source converters (VSCs) operate loads in conditions of current continuity. The only requirement is that the modules are based on half-bridge architectures, possibly synchronous, such as buck, boost, half-bridge, full-bridge and three-phase bridges. The proposed controller can work with small (few microhenries) series inductors, mostly comparable with the stray inductance already existing in the wiring. Each regulator adjusts the pulse-width modulation (PWM) of a given converter based only on its own output current. Each PWM pattern is shifted on the nanosecond time scale using a peculiarly inexpensive software modulator. The overall control action allows achieving the synchronous operation of all converters at modulation frequency, thus suppressing the circulating current. The control strategy is mathematically designed through novel models, and experimentally validated employing three DC-DC converters. The study demonstrates (i) the feasibility and robustness of the method to compensate for both phase and frequency errors among the units, (ii) the capability of the controller to cope with the inherent parameter mismatch among the modules, and (iii) its ability to operate in tandem with a load balancing regulator.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10621445","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Reduced Switches Nine-Level Inverter Applicable in Aircraft Ground Power Unit","authors":"Reza Ebrahimi;Hossein Madadi Kojabadi;Hamed Jafari Kaleybar","doi":"10.1109/OJPEL.2024.3436693","DOIUrl":"10.1109/OJPEL.2024.3436693","url":null,"abstract":"Ground power unit (GPU) converters are often required to efficiently manage power distribution in various ground-based applications, necessitating designs that balance performance, and cost-effectiveness. In this paper, a novel nine-level output converter using a single voltage source, 8 unidirectional and one bidirectional MOSFET switches, and two capacitors has been presented to utilize in GPUs. A simple modulation algorithm (PWM) has been applied to achieve a THD of 3.1% on the output voltage at 115/200 V and 400 Hz without the need for additional filtering. With a relatively small output filter, the THD is further reduced to less than 1%. The proposed converter utilized a lower number of devices to output a nine-level staircase in comparison to existing converters. Additionally, the proposed converter employs inherent self-voltage balancing for capacitor voltages, thereby simplifying the control algorithm. In this paper, the topology analysis, modulation algorithm, capacitor calculation, loss, efficiency, and performance analysis of the proposed topology have been presented. The proposed circuit has been compared to recently published papers in terms of switch, capacitor, diode, and source numbers. The theoretical and experimental performance of the topology has been verified by simulation on PSIM software and experimental setup.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10620626","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Digital Twin Development of a Testing Grid Using a Grid Analyzer","authors":"Derk Gonschor;Jonas Steffen;Juan Alvaro Montoya Perez;Christian Bendfeld;Detlef Naundorf;Philipp Kost;Christian Aigner;Florian Füllgraf;Ron Brandl;Marco Jung","doi":"10.1109/OJPEL.2024.3436510","DOIUrl":"10.1109/OJPEL.2024.3436510","url":null,"abstract":"The recent transformation of the energy sector brings new challenges in areas such as supply security, efficiency, and reliability. Especially the increase of decentralized power plants leads to a more complex energy system and an increasing complexity. This requires expansion and digitization of the power grid as well as an initiative-taking operation of the grid operator. To investigate such complex systems and its phenomena, modern development methods such as real-time simulation or digital twins (DT) can be used. In this approach a digital replica of the real-world system, a grid section, is developed, which can represent or predict the behavior of the real distribution grid. For this, a model of the real-world system is derived and implemented in a co-simulation environment, in which it receives data via an analyzer or measurement system from the grid model. This paper focuses on the development of the digital twin of a testing grid and a grid analyzer for the measurement. With the digital twin of the testing grid, a first approach is achieved in a real-time capable environment showing the functionalities and interactions of a digital twin. Subsequently the development of the digital twin model is explained, and the results are discussed.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10621013","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact Two-Phase Immersion Cooling With Dielectric Fluid for PCB-Based Power Electronics","authors":"Aleksandar Ristic-Smith;Daniel J. Rogers","doi":"10.1109/OJPEL.2024.3432989","DOIUrl":"10.1109/OJPEL.2024.3432989","url":null,"abstract":"This paper explores two-phase immersion cooling using sealed enclosures of dielectric fluid as a technique to achieve compact, power dense converters on a single printed circuit board (PCB). The proposed approach employs passive circulation of the fluid and does not introduce system complexity beyond a heat exchanger required to condense the vapour. A test apparatus representing six 650 V, 150 A semiconductor switches in an inverter rejecting heat to a 65\u0000<inline-formula><tex-math>$,^{circ }$</tex-math></inline-formula>\u0000C water cooling loop is developed. Pool boiling experiments on a flat surface in Novec 7000 dielectric fluid demonstrate critical heat flux of 43 W cm\u0000<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula>\u0000 at a saturation temperature of 94\u0000<inline-formula><tex-math>$,^{circ }$</tex-math></inline-formula>\u0000C and a corresponding pressure of 593 kPa. By augmenting the surface with pin fins (representative of a heat spreader attached to a switch) and grit blasting to improve the surface micro-geometry, the maximum heat transfer coefficient increased from 1.5 W cm\u0000<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula>\u0000 K\u0000<inline-formula><tex-math>$^{-1}$</tex-math></inline-formula>\u0000 to 3.4 W cm\u0000<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula>\u0000 K\u0000<inline-formula><tex-math>$^{-1}$</tex-math></inline-formula>\u0000 with a corresponding reduction in switch temperature from 125\u0000<inline-formula><tex-math>$,^{circ }$</tex-math></inline-formula>\u0000C to 107\u0000<inline-formula><tex-math>$,^{circ }$</tex-math></inline-formula>\u0000C at the total power dissipation of 186 W. A practical implementation with comparable thermal performance to the experimental apparatus but minimised volume of 0.12 L is presented. This yields a Cooling System Performance Index of 37 WL\u0000<inline-formula><tex-math>$^{-1}$</tex-math></inline-formula>\u0000 K\u0000<inline-formula><tex-math>$^{-1}$</tex-math></inline-formula>\u0000, including the heat exchanger and printed circuit board with switches, decoupling capacitors and gate drivers.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612781","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141781768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Comparison of Isolated High Step-up DC-DC Converters for Low Power Application","authors":"Saeed Pourjafar;Hossein Afshari;Parham Mohseni;Oleksandr Husev;Oleksandr Matiushkin;Noman Shabbir","doi":"10.1109/OJPEL.2024.3433554","DOIUrl":"10.1109/OJPEL.2024.3433554","url":null,"abstract":"In this paper comprehensive evaluations of isolated high step-up dc-dc topologies have been investigated. These converters are especially well suited for distributed generation systems utilizing renewable or alternative energy sources that need a wide input voltage range with load regulation. With this in mind, this work primarily concentrates on comparative analysis of various isolated configurations employed in possible industry applications. Consequently, several isolated structures, including flyback, forward, push-pull, and full bridge and other similar solutions have been carried out in the literature. For the purpose of comparative and theoretical analysis, some of the circuit parameters are considered, which include voltage conversion ratio, semiconductor element voltage stress, component size, and conduction and switching losses. Furthermore, the selected configurations have been discussed in terms of cost estimation and financial feasibility. In addition, the design procedure and experimental prototypes of the available solutions with the main results are presented. Derived from this investigation, the authors provide a guide to help researchers to identify different isolated topologies with wide input voltage range and galvanic isolation for prospective research directions within this area.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609489","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141781771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Output Terminations on Common-Mode Conducted Emissions Evaluation of Interface Converters","authors":"Christopher D. New;Andrew N. Lemmon;Aaron D. Brovont","doi":"10.1109/OJPEL.2024.3433605","DOIUrl":"10.1109/OJPEL.2024.3433605","url":null,"abstract":"Current conducted emissions standards provide considerable flexibility in the handling of interface converters, which are of increasing importance for the design and implementation of microgrids. Of particular interest herein is the approach selected for terminating the output ports of such converters during conducted emissions qualification testing. This article provides a theoretical treatment of an interface converter consisting of a SiC-based single-phase inverter in a custom-built testbed for evaluating conducted emissions. The accompanying analysis demonstrates that the selection of output terminations plays a significant role in determining the resulting emissions, with a difference of up to 40 dB observed in the relevant emissions metrics. These predictions are validated with a set of empirical studies. The dependence on output termination selection is emphasized further in deployed systems, which are not influenced by the presence of compliance measurement equipment. In this configuration, the common-mode resonance of the system is shown to elevate peak emissions due to reduced damping. Overall, this paper highlights an opportunity to improve emissions standards with respect to interface converters by standardizing output terminations, particularly in view of the increased high-frequency emissions produced by systems implemented with wide band-gap technology.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609520","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141781770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Zero-Voltage Switching and Natural Voltage Balancing of a 3 kW 1 MHz Input-Series-Output-Parallel GaN LLC Converter","authors":"Qingxuan Ma;Qingyun Huang;Alex Q. Huang","doi":"10.1109/OJPEL.2024.3433562","DOIUrl":"10.1109/OJPEL.2024.3433562","url":null,"abstract":"Input-Series-Output-Parallel (ISOP) LLC converters have the capability to leverage lower voltage semiconductor devices, thereby enabling applications with higher voltage requirements. The primary advantages lie in enhanced efficiency and power density attributed to improved device performance. Given the utilization of multiple modular LLC converters, the potential impact of component parameter mismatch becomes a significant concern. Specifically, issues related to input voltage sharing (IVS) and device zero voltage switching (ZVS) are critical considerations. This paper develops a precise mathematical model during deadtime to determine ZVS boundaries, taking into account parameter mismatches. Within the developed boundaries, all LLC sub-modules are assured of ZVS operation. To assess IVS performance, a mathematical model is formulated using the first harmonic approximation (FHA) equivalent circuit. To validate the proposed modeling and analysis, a 3 kW 1 MHz GaN-based ISOP LLC is constructed, comprising four modular 750W-LLC units. Experimental results showcase successful ZVS operations and natural voltage balancing of the ISOP LLC converter across a broad range of parameter mismatches.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141781769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A General Analytical Formulation for LCL Filter Design for Grid-Connected PWM-Driven Cascaded H-Bridge Inverters","authors":"Giuseppe Schettino;Giuseppe Sorrentino;Gioacchino Scaglione;Claudio Nevoloso;Antonino Oscar Di Tommaso;Rosario Miceli","doi":"10.1109/OJPEL.2024.3432990","DOIUrl":"10.1109/OJPEL.2024.3432990","url":null,"abstract":"This paper proposes a general analytical formulation for LCL filter design for grid-connected PWM-driven cascaded H-bridge inverters. The novelty of this work deals with providing some easy-of-use analytical expressions that allow for properly sizing the filter inductances and capacitance values considering the number of voltage levels, the DC-link voltage, the adopted multicarrier pulse width modulation strategy, and the switching frequency. Although multilevel inverters performance strongly depends on the adopted modulation strategy and switching frequency, a general mathematical formulation that allows for properly sizing the LCL filter by considering such parameters simultaneously is currently missing. The proposed approach is generalized for the most adopted multicarrier pulse width modulation strategies. To validate the proposed approach, an extended investigation analysis is performed by hardware-in-the-loop real-time tests. According to international standards EN50160 and IEEE Std 1547–2018, the voltage total harmonic distortion and current total rated distortion are adopted to evaluate the LCL filter performance. Tests are carried out in several working conditions, defined in terms of provided apparent power and power factor values. Finally, the proposed analytical formulation is adopted to formulate an optimized LCL filter design algorithm that allows for matching the standard requirements without oversizing the filter parameters.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10608387","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141781773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Two-Switch Ultrahigh Step-Up DC–DC Converterer With Low Input Current Ripple and Low Switch Voltage Stress","authors":"Vahid Abbasi;Mohammad Mehdi Kashani;Milad Rezaie;Dylan Dah-Chuan Lu","doi":"10.1109/OJPEL.2024.3432628","DOIUrl":"10.1109/OJPEL.2024.3432628","url":null,"abstract":"Existing high step-up DC-DC converters suffer from various issues, including limited voltage gain, high voltage stress on semiconductors, and high current ripple. To solve these issues, a step-up converter with ultrahigh gain (40x at 50% duty cycle for a turn ratio of 2) composed of two boosting stages, a three-winding coupled inductor, a charge pump and a switched capacitor is presented. The other positive structural properties of the proposed converter are the low current ripple of its input source, the low voltage stress on its switches and most of the diodes, and the existence of a common ground between the input and output sides. The circuit configuration of the proposed converter requires a smaller series inductor due to its ability to achieve the same voltage gain as similar converters with a smaller duty cycle. Additionally, the proposed converter exhibits a low input current ripple, further distinguishing it from similar converters. The coupled inductor is placed in a way to effectively decreases voltage stress on the switches. The converter is compared with the other high step-up converters from different viewpoints demonstrating its superiorities including power density and cost-effectiveness. An experimental prototype, rated at 240 W with 20 V input voltage and 400 V output voltage, is reported to validate the theoretical analysis, performance quality, and dynamic response of the converter.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10607863","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141781772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of a Generalized Multilevel SVM and Capacitor Voltage Balancing Strategy for Multiphase Three-Level NPC Converters","authors":"Mahdi Homaeinezhad;Omid Beik","doi":"10.1109/OJPEL.2024.3429412","DOIUrl":"10.1109/OJPEL.2024.3429412","url":null,"abstract":"This paper proposes a generalized space vector modulation (SVM) strategy for 3-level neutral-point-clamped (NPC) converters. The proposed strategy, here referred to as multiphase 3-level SVM (MP3L-SVM), is developed as a generic modulation technique applicable for 3-level NPC converters with any number of phases, while for showcasing in this paper the proposed MP3L-SVM is applied to a wind turbine with a direct drive multiphase permanent magnet generator (PMG) whose output is rectified using a 3-level NPC converter before connection to a high-voltage DC (HVDC) grid. A key challenge in 3-level NPC converters is maintaining a balanced voltage across the HVDC-link capacitors, particularly at low speeds. To address this issue, the paper integrates the proposed MP3L-SVM strategy with a voltage balancing algorithm (VBA), which mitigates capacitor voltage imbalances by choosing the three nearest switching states that result in minimal energy deviations across the capacitors. The paper discusses the mathematical modeling of a multiphase PMG interfaced to a 3-level NPC and derives generalized models that govern the proposed strategy based on a visual space vector diagram (SVD). Analytical models are validated through simulations across various 3-level NPC configurations, including 3-phase, 6-phase, and 9-phase NPC converters. Further, the analytical models and simulation results are validated by test results from a scaled-down laboratory prototype 3-level NPC converter that has been prototyped in-house.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":null,"pages":null},"PeriodicalIF":5.0,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10599858","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141719425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}