IEEE open journal of power electronics最新文献

{"title":"Rapid State-of-Power Estimation of Lithium-Ion Battery Packs in DC Microgrids","authors":"Leevi Lignell;Minh Tran;Tomi Roinila","doi":"10.1109/OJPEL.2026.3690767","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3690767","url":null,"abstract":"Lithium-ion (Li-ion) batteries are widely used as energy storage systems in DC microgrids. Effective and lifetime-prolonging operation of Li-ion batteries requires continuous monitoring and control of their operating conditions. One important state parameter in this context is the state of power (SOP), which describes the battery’s ability to supply a load under specified constraints. In this work, an SOP estimation method based on rapid online battery impedance measurements is proposed. The method utilizes impedance measurement data to evaluate the effects of both internal resistance and charge accumulation on the battery cell terminal voltage. The proposed SOP estimation approach is independent of prior battery measurement data and does not rely on the estimation of other state parameters, such as the state of charge (SOC). Experimental measurements on commercial Li-ion battery cells using bi-directional load currents and peak current pulses were conducted to evaluate the performance of the proposed SOP estimation method. The method predicts the battery voltage with a maximum root mean square error of 13.07 mV across all bi-directional current tests and predicts the peak current pulse voltage with a root mean square error of 5.27 mV. This work is a revised and extended version of a presentation at ICDCM [L. Lignell] et al., 2025.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1540-1553"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11509348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147937511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System-Level Efficiency Study of Modular DC/DC and Fuel Cell Stack Series–Parallel Configurations","authors":"Erdem Asa;Vivek A. Sujan;Omer C. Onar","doi":"10.1109/OJPEL.2026.3680915","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3680915","url":null,"abstract":"This paper presents a system-level efficiency study of modular DC/DC converter and fuel cell stack configurations under series, parallel, and series–parallel connections. The investigation considers selected DC/DC converter topologies, including isolated and non-isolated architectures, boost, non-inverting buck-boost, and resonant converters, integrated with commercially available fuel cell stacks, including the Accelera FCE150, Ballard FCgen-HPS, and Toyota TFCM2. DC/DC converter modules are evaluated in modular configurations rated at 60 kW and 90 kW and two distinct output voltage ranges, specifically 580–730 V and 780–930 V, examining how different interconnection schemes impact overall system efficiency. The converters are evaluated under full load (100%), partial load (66%), and light load (33%) conditions, providing a comprehensive assessment of efficiency and operational characteristics across varying power demands. Approximately two-thousand efficiency data points are obtained from laboratory prototype–level component measurements and validated design evaluations across multiple converter topologies, modular configurations, voltage ranges, and load conditions, providing a robust dataset for comparative system-level efficiency analysis. The results highlight the effects of modularity and topology selection on system-level efficiency, offering a “playbook” framework for designers to select appropriate DC/DC converter arrangements and fuel cell stack connections for series, parallel, or hybrid configurations based on efficiency considerations.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1295-1308"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11474928","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Digital Cross–Coupled Phase Control to Maintain 180° Interleaving in BCM/DCM Boost PFC","authors":"Ming-Chang Tsou;Hung-Ching Lee;Jheng-Ruei Jhih","doi":"10.1109/OJPEL.2026.3685959","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3685959","url":null,"abstract":"This paper presents a cross-coupled, closed-loop digital phase control strategy for two-phase interleaved boost power factor correction (PFC) converters operating in boundary conduction mode (BCM) and discontinuous conduction mode (DCM). Implemented on a DE1-SoC platform, the proposed control scheme utilizes a non-master-slave architecture that integrates per-cycle period measurement with a predictive scheduling algorithm. A key advantage of this approach is its capability to achieve deadbeat-like phase response and maintain a highly stable 180° phase shift. Unlike open-loop methods, the proposed controller derives timing constraints from the slower phase to effectively mitigate phase drifting caused by component mismatches and switching frequency variations. Experimental results from a 300 W prototype confirm the design's effectiveness: the precise interleaving maximizes input current ripple cancellation, achieving a 50% reduction in peak-to-peak ripple compared to non-interleaved operation. This stability significantly reduces stress on passive components and optimizes electromagnetic interference (EMI) performance, validating the solution for compact, high-performance front-end power supplies.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1339-1348"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11488666","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synchronous Switching Scheme - Bringing Modular Fault Tolerance to Power Converters","authors":"Aditya Shirodkar;Satish Naik Banavath;Andrii Chub;Riccardo Mandrioli;Mattia Ricco;Dimitri Vinnikov","doi":"10.1109/OJPEL.2026.3683136","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3683136","url":null,"abstract":"Various critical applications in domains such as electric vehicles, space technology, defence, data-centers and microgrids require high power, uninterruptible and high reliability power electronic converters. This paper focusses on developing a highly modular and topology independent fault tolerant approach, making it an attractive solution for industrial applications. The paper validates the proposed approach through PLECS simulation of a 400 V and 5 kW full-bridge forward converter, and performs hardware validation at 400 V DC bus voltage as well. Further, the paper thoroughly analyses the losses, efficiency, reliability and mean time to failure of the proposed fault tolerance solution, and proves its effectiveness across various key factors in comparison to existing approaches in literature.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1265-1280"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11479841","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147737136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Cauer-Foster Integrated Thermal Network Model for Multi-Chip SiC Power Modules Considering Temperature-Dependent Material Properties","authors":"Shuoyu Ye;Jingyang Hu;Guofu Chen;Chushan Li;Haoze Luo;Wuhua Li;Xiangning He;Francesco Iannuzzo","doi":"10.1109/OJPEL.2026.3699397","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3699397","url":null,"abstract":"This paper proposes a thermal network model (TNM) for multi-chip silicon carbide (SiC) power modules, which effectively incorporates temperature-dependent material properties and thermal cross-coupling (TCC) effects among parallel chips. The model adopts a hybrid three-dimensional (3-D) structure, combining a Cauer network for internal layer-wise heat conduction with a Foster network for external dissipation paths, enabling accurate and efficient electro-thermal simulations. A systematic parameter identification method is developed, leveraging finite element method (FEM) simulations to extract thermal conductance and thermal capacitance parameters through non-negative least-squares optimization and transient response fitting, with the temperature dependence of material properties fully considered. Steady-state and transient validations against FEM results show excellent consistency under different power loss levels and boundary conditions. For experimental validation, a dedicated test bench for SiC module junction temperature measurement is built, combining fiber-optic temperature sensing and thermal imaging techniques. The slight experimental deviations with a maximum error of less than 2.5 °C demonstrate that the model can accurately track the measured transient junction temperature of the module.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1865-1877"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11544054","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Review of DC-DC Converters for Modular Solid-State Transformers: Challenges, Comparative Analysis, and Design","authors":"João Victor G. França;Levy F. Costa;Samuel S. Queiroz;Binhong Cao;Zhicheng Guo","doi":"10.1109/OJPEL.2026.3699737","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3699737","url":null,"abstract":"Solid-State Transformer (SST) technology has advanced significantly in recent decades, driven by the development of wide-bandgap semiconductors, progress in magnetic component design, and continuous optimization of power converter topologies. The modular SST architecture employs multiple power electronic building blocks (PEBBs) that constitute the DC-DC stage. Selecting the most suitable PEBB topology is critical to the overall performance of the SST and remains an open research question. This paper presents a comprehensive overview of the main requirements and challenges associated with the PEBB and reviews the most suitable DC-DC converter topologies for modular SST applications, including a comparative analysis of efficiencies reported in the literature in recent years. The most promising topologies are then identified, and a case study with a detailed design methodology is presented. A review of the latest advancements in medium-frequency transformer technology, which represents a key bottleneck in DC–DC converter design, is also included. Finally, experimental validations considering three different PEBB topologies are performed, achieving high efficiency (98.55% peak), confirming its feasibility for modular SST systems.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1846-1864"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11548666","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel DC-DC Active Balancer of Currents for Bipolar DC Power Grids","authors":"Vitor Monteiro;Pedro Brito;Sergio Coelho;Saghir Amin;Muhammad Awais;Joao L. Afonso","doi":"10.1109/OJPEL.2026.3726835","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3726835","url":null,"abstract":"DC Power Grids (DCPGs) are becoming more important, mostly due to the inherent DC characterization of new sources and load technologies, like renewables and electric vehicles. Remarkably, thanks to advances in power electronics converters and control algorithms, bipolar DCPGs are attaining additional prevalence, which results mainly from the increasing efficiency and power density of power converters, but also because DCPG avoid some characteristic power quality problems of the AC power systems. The voltages of the bipolar DCPG should be balanced in the main source by the AC-DC power converter, or by additional converters with the single objective of voltage balancing; however, independently of the voltage balancing and depending on the loads, which can be linked through two-wires or three-wires, current unbalances may occur. In this context, this paper proposes a novel three-wire DC-DC converter operating as an Active Balancer of Currents (ABC), which is linked in parallel to the bipolar DCPG through the three-wires of the point of common coupling (PCC), to ensure balanced currents in the main source. The proposed three-wire DC-DC converter operating as an ABC has a three-wire interface and offers the possibility of a bidirectional power operation, ensuring the compensation of all scenarios of current unbalances. Since it is linked in parallel to the bipolar DCPG, it controls and balances directly the current between wires, ensuring balanced currents on the source side and zero current on the neutral wire. A laboratory prototype was developed and experimental results were obtained. The validation was carried out considering distinctive current unbalances, both positive and negative, as well as sudden variations, verifying the correct operation of the proposed three-wire DC-DC converter functioning as an ABC.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"2544-2558"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11663396","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Management and Experimental Validation of a Copper-Inlay PCB for SiC MOSFETs in High-Power EV Fast Chargers","authors":"Muhammad Awais;Saghir Amin;Francisco P. Brito;Nuno Costa;João L. Afonso;Vitor Monteiro","doi":"10.1109/OJPEL.2026.3672717","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3672717","url":null,"abstract":"Efficient thermal management is essential to ensure reliability and performance in high-power electric vehicle (EV) fast-charging converters employing silicon carbide (SiC) MOSFETs. SiC MOSFETs are widely adopted in next-generation power converters due to their high efficiency, fast switching capability, and ability to operate at high temperatures. This paper presents an integrated thermal management strategy combining a copper-inlay printed circuit board (PCB) with a hybrid aluminum cold plate containing embedded copper pipes to improve heat spreading and SiC MOSFET die-to-coolant thermal performance. A complete analytical and simulation-based framework is developed to evaluate the thermal resistance of each layer in the conduction path, starting with the SiC MOSFET die, then the solder joint, copper inlay, thermal interface material (TIM), and cold plate, and finally the circulating coolant. The power-loss profiles of the SiC MOSFETs and diodes were calculated using analytical switching-loss and conduction loss models. Finite-element simulations in COMSOL Multiphysics quantify the internal temperature distribution and evaluate the impact of PCB configuration, TIM conductivity, and coolant flow rate on the SiC MOSFET die and package surface temperature. Results show that the copper-inlay PCB reduces thermal resistance by more than 30 percent compared to via-based boards, lowering the MOSFET package surface temperature from approximately 130 °C to 102 °C under identical power dissipation. Parametric analysis demonstrates that selecting an optimized TIM conductivity of 5 W/(m·K) and a coolant flow rate of 1 GPM reduces the SiC MOSFET die temperature from 102 °C to about 41 °C. Experimental validation using a fabricated prototype showed strong correlation with simulation results in terms of spatial temperature distribution and hotspot locations, confirming the accuracy of the thermal model. The proposed multilayer copper-inlay and cold-plate configuration provides a compact, reliable, and scalable thermal solution for next-generation SiC-based high-power EV fast-charging converters.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1006-1020"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11429580","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extending the Controllability of Minimized VA Rating Wireless Power Transfer Systems Operating in Restricted Sub-Resonant Frequency Region","authors":"Andrey Vulfovich;Alon Kuperman","doi":"10.1109/OJPEL.2026.3673868","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3673868","url":null,"abstract":"Sub-resonant frequency (SRF) operation of inductive wireless power transfer systems (IWPTS) allows attaining constant current (CC) output under varying coupling and output voltage conditions while minimizing transmitter volt-ampere (VA) rating. Unfortunately, SRF-operated IWPTS equipped with diode rectifier-based receivers are uncapable of reducing the output current freely below rated value. This drawback prevents their employment in applications where a wide range of output currents is essential (e.g., Li-ion battery charging, characterized by rated constant current output during constant current stage and gradually decreasing current output down to a near-zero value during constant voltage stage). To bridge the gap, this work proposes equipping the IWPTS with a semi-active rectifier (SAR) based receiver and utilizing SRF control of the transmitter in conjunction with phase-shift (PS) control of the receiver to attain full system controllability under different coupling and varying output voltage conditions. Feasibility of the proposed methodology is successfully validated by experiments.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"1037-1047"},"PeriodicalIF":3.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11434506","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Phase-Compensated Multi-Resonant Control for Inverter Applications","authors":"Moria Sassonker Elkayam;Dmitri Vinnikov","doi":"10.1109/OJPEL.2026.3663332","DOIUrl":"https://doi.org/10.1109/OJPEL.2026.3663332","url":null,"abstract":"This paper presents an extended current control framework for grid-connected power converters based on a phase-compensated multi-resonant controller. The proposed approach extends a previously introduced single-resonant control scheme proposed in (Elkayam et al., 2025) to a multi-resonant structure capable of compensating multiple harmonic components while maintaining robust stability under digital delay. Selective phase compensation is applied only to the final resonant term, avoiding anti-resonant effects commonly associated with full compensation schemes. To address practical implementation challenges, an artificial intelligence-based evaluation framework is introduced to automate the selection of discretization methods for individual resonant components, ensuring high-fidelity digital realization. The stability and performance of the proposed controller are analyzed using frequency-domain and stability criteria. Experimental validation is carried out on two different inverter topologies, namely a three-level three-phase T-type converter and a single-phase H-bridge inverter, demonstrating accurate current tracking, effective harmonic suppression, and robust operation under practical conditions.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"7 ","pages":"670-682"},"PeriodicalIF":4.8,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11389130","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148482868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}