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Proceedings. Design Automation Conference最新文献

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Cyber-physical systems: The next computing revolution 网络物理系统:下一次计算革命
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837461
R. Rajkumar, Insup Lee, L. Sha, J. Stankovic
{"title":"Cyber-physical systems: The next computing revolution","authors":"R. Rajkumar, Insup Lee, L. Sha, J. Stankovic","doi":"10.1145/1837274.1837461","DOIUrl":"https://doi.org/10.1145/1837274.1837461","url":null,"abstract":"Cyber-physical systems (CPS) are physical and engineered systems whose operations are monitored, coordinated, controlled and integrated by a computing and communication core. Just as the internet transformed how humans interact with one another, cyber-physical systems will transform how we interact with the physical world around us. Many grand challenges await in the economically vital domains of transportation, health-care, manufacturing, agriculture, energy, defense, aerospace and buildings. The design, construction and verification of cyber-physical systems pose a multitude of technical challenges that must be addressed by a cross-disciplinary community of researchers and educators.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"36 1","pages":"731-736"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80149389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1772
Circuit modeling for practical many-core architecture design exploration 电路建模对实用多核架构设计的探索
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837432
D. Truong, B. Baas
{"title":"Circuit modeling for practical many-core architecture design exploration","authors":"D. Truong, B. Baas","doi":"10.1145/1837274.1837432","DOIUrl":"https://doi.org/10.1145/1837274.1837432","url":null,"abstract":"Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor architecture to motivate a circuit based design approach applied to a computer architecture problem. A test chip with DVFS capable processors is used to explore our ideas through software implementation.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"20 1","pages":"627-628"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76556285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Global routing and track assignment for flip-chip designs 倒装芯片设计的全局路由和跟踪分配
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837298
Xiaodong Liu, Yifan Zhang, G. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng
{"title":"Global routing and track assignment for flip-chip designs","authors":"Xiaodong Liu, Yifan Zhang, G. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng","doi":"10.1145/1837274.1837298","DOIUrl":"https://doi.org/10.1145/1837274.1837298","url":null,"abstract":"This paper describes a solution for global routing and track assignment of flip-chip I/O nets. Voronoi Diagram (VD) is used to partition the open routing space and the geometrical properties of VD graph are exploited to create global routing channels with capacity and congestion considerations. A network flow algorithm is used to achieve optimal global routing. The regularity of the flip-chip bump placement is observed and allows us to reduce the size of global routing channel graph by over 50% to speed up computation. A track assignment algorithm avoids crossing wires before completing the final route with a detailed router. Experiment results using actual silicon chip data demonstrate that our solution achieves good quality of results compared to an implementation used in a commercial tool. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids — Layout, Placement and Routing General Terms: Algorithms, Design","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"17 1","pages":"90-93"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88024732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs 利用可重构性实现数字锁相环的低成本原位测试和监测
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837507
L. Yin, Peng Li
{"title":"Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs","authors":"L. Yin, Peng Li","doi":"10.1145/1837274.1837507","DOIUrl":"https://doi.org/10.1145/1837274.1837507","url":null,"abstract":"We exploit the reconfigurability of recent all-digital PLL designs to provide novel in-situ output jitter test and diagnosis abilities under multiple parametric variations of key analog building blocks. Digital signatures are collected and processed under specifically designed loop filter configurations to facilitate low-cost high-accuracy performance prediction and diagnosis.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"63 1","pages":"929-934"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88314060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
LATA: A latency and Throughput-Aware packet processing system 延迟和吞吐量感知包处理系统
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837286
Jilong Kuang, L. Bhuyan
{"title":"LATA: A latency and Throughput-Aware packet processing system","authors":"Jilong Kuang, L. Bhuyan","doi":"10.1145/1837274.1837286","DOIUrl":"https://doi.org/10.1145/1837274.1837286","url":null,"abstract":"Current packet processing systems only aim at producing high throughput without considering packet latency reduction. For many real-time embedded network applications, it is essential that the processing time not exceed a given threshold. In this paper, we propose LATA, a LAtency and Throughput-Aware packet processing system for multicore architectures. Based on parallel pipeline core topology, LATA can satisfy the latency constraint and produce high throughput by exploiting fine-grained task-level parallelism. We implement LATA on an Intel machine with two Quad-Core Xeon E5335 processors and compare it with four other systems (Parallel, Greedy, Random and Bipar) for six network applications. LATA exhibits an average of 36.5% reduction of latency and a maximum of 62.2% reduction of latency for URL over Random with comparable throughput performance.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"10 1","pages":"36-41"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88987418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An efficient algorithm to verify generalized false paths 一种有效的验证广义假路径的算法
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837321
O. Coudert
{"title":"An efficient algorithm to verify generalized false paths","authors":"O. Coudert","doi":"10.1145/1837274.1837321","DOIUrl":"https://doi.org/10.1145/1837274.1837321","url":null,"abstract":"Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem because of the inherent computational cost, and because in practice false paths are not specified one full path at a time. Instead designers use generalized false paths, which represent a set of paths. For instance the SDC format (Synopsys Design Constraint) specifies false path exceptions using a “-from -through -to” syntax that applies on sets of pins, often using wildcards to denote these sets. This represents many (usually hundreds to thousands) actual full paths. This paper proposes a method to verify generalized false paths in a very efficient manner. It is shown to be about 10x faster than the current state-of-the-art, making false path verification an overnight task or less for multi-million gate designs.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"2 1","pages":"188-193"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86962436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Model-based functional verification 基于模型的功能验证
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837380
K. Kundert, Henry Chang
{"title":"Model-based functional verification","authors":"K. Kundert, Henry Chang","doi":"10.1145/1837274.1837380","DOIUrl":"https://doi.org/10.1145/1837274.1837380","url":null,"abstract":"Just as digital design did 15 years ago; analog design has now readied a transition. The move to CMOS has made analog circuits more functionally complex, and that complexity leads naturally to functional errors in the designs, which in turn leads to respins and delays. And just as digital designers did 15 years ago, analog designers are beginning to realize that they need to employ a rigorous functional verification methodology. We present the basic concepts of analog verification that can be used to find a wide variety of functional errors in complex mixed-signal integrated circuits.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"30 1","pages":"421-424"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83616136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
What input-language is the best choice for high level synthesis (HLS)? 哪种输入语言是高级合成(HLS)的最佳选择?
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837489
D. Gajski, T. Austin, Steve Svoboda
{"title":"What input-language is the best choice for high level synthesis (HLS)?","authors":"D. Gajski, T. Austin, Steve Svoboda","doi":"10.1145/1837274.1837489","DOIUrl":"https://doi.org/10.1145/1837274.1837489","url":null,"abstract":"As of 2010, over 30 of the world's top semiconductor / systems companies have adopted HLS. In 2009, SOCs tape-outs containing IPs developed using HLS exceeded 50 for the first time. Now that the practicality and value of HLS is established, engineers are turning to the question of “what input-language works best?” The answer is critical because it drives key decisions regarding the tool/methodology infrastructure companies will create around this new flow. ANSI-C/C++ advocates cite ease-of-learning, simulation speed. SystemC advocates make similar claims, and point to SystemC's hardware-oriented features. Proponents of BSV (Bluespec SystemVerilog) claim that language enhances architectural transparency and control. To maximize the benefits of HLS, companies must consider many factors and tradeoffs.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"1 1","pages":"857-858"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89857952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
On-die power grids: The missing link 片上电网:缺失的一环
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837511
E. Chiprout
{"title":"On-die power grids: The missing link","authors":"E. Chiprout","doi":"10.1145/1837274.1837511","DOIUrl":"https://doi.org/10.1145/1837274.1837511","url":null,"abstract":"Power grids with die-scale dimensions operate in a transient manner that is difficult to predict compared to larger power grids. Given a single excitation and a detailed model one can come to understand the dynamic effects occurring inside the die in terms of localized voltage droop scenarios. However, a major portion of understanding on-die power grids has to do with modeling the current stimulus pre-silicon for design purposes as well as generating a set of activities (via instructions) post-silicon in order to excite the worst case voltage droop. Any chip, especially a microprocessor, contains so many potential state transitions that it is not possible to simulate or enumerate all of them. A spectral-based learning and optimization method can alleviate this problem pre-silicon, while a micro-architectural based test generation scheme can help alleviate the problem post silicon.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"14 1","pages":"940-945"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78502080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
RDE-based transistor-level gate simulation for statistical static timing analysis 基于rde的晶体管级栅极仿真统计静态时序分析
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837473
Qin Tang, A. Zjajo, Michel Berkelaar, Nick van der Meijs
{"title":"RDE-based transistor-level gate simulation for statistical static timing analysis","authors":"Qin Tang, A. Zjajo, Michel Berkelaar, Nick van der Meijs","doi":"10.1145/1837274.1837473","DOIUrl":"https://doi.org/10.1145/1837274.1837473","url":null,"abstract":"Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-level models for standard cells, which have accuracy problems as well as require massive amounts of CPU time in Monte-Carlo (MC) simulation. In this paper we present a new transistor-level non-Monte Carlo statistical analysis method based on solving random differential equations (RDE) computed from modified nodal analysis (MNA). In order to maintain both high accuracy and efficiency, we introduce a simplified statistical transistor model for 45nm technology and below. The model is combined with our new simulation-like engine which can do both implicit non-MC statistical simulation and deterministic simulation fast and accurately. The statistics of delay and slew are calculated by means of the proposed analysis method. Experiments show the proposed method is both run time efficient and very accurate.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"2023 1","pages":"787-792"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72856548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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