Proceedings. Design Automation Conference最新文献_第6页

What's smart about the smart grid? 智能电网的聪明之处是什么?

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837510

I. Hiskens

引用次数: 24

Clock tree synthesis under aggressive buffer insertion 主动缓冲区插入下的时钟树合成

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837297

Ying-Yu Chen, Chen Dong, Deming Chen

引用次数: 21

Trace-driven optimization of networks-on-chip configurations 跟踪驱动的片上网络配置优化

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837384

A. Kahng, Bill Lin, K. Samadi, R. Ramanujam

{"title":"Trace-driven optimization of networks-on-chip configurations","authors":"A. Kahng, Bill Lin, K. Samadi, R. Ramanujam","doi":"10.1145/1837274.1837384","DOIUrl":"https://doi.org/10.1145/1837274.1837384","url":null,"abstract":"Networks-on-chip (NoCs) are becoming increasingly important in general-purpose and application-specific multi-core designs. Although uniform router configurations are appropriate for general-purpose NoCs, router configurations for application-specific NoCs can be non-uniformly optimized to application-specific traffic characteristics. In this paper, we specifically consider the problem of virtual channel (VC) allocation in application-specific NoCs. Prior solutions to this problem have been average-rate driven. However, average-rate models are poor representations of real application traffic, and can lead to designs that are poorly matched to the application. We propose an alternate trace-driven paradigm in which configuration of NoCs is driven by application traces. We propose two simple greedy trace-driven VC allocation schemes. Compared to uniform allocation, we observe up to 51% reduction in the number of VCs under a given average packet latency constraint, or up to 74% reduction in average packet latency with same number of VCs. Our results suggest that average-rate driven methods cannot effectively select appropriate links for VC allocation because they fail to consider the impact of traffic bursts. As a case study, we compare our proposed approach with an existing average-rate driven method and observe up to 35% reduction in the number of VCs for a given target latency.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"25 1","pages":"437-442"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84626848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Crosstalk noise and bit error rate analysis for optical network-on-chip 片上光网络串扰噪声和误码率分析

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837441

Yiyuan Xie, M. Nikdast, Jiang Xu, Wei Zhang, Qi Li, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Weichen Liu

引用次数: 128

Thermal monitoring of real processors: Techniques for sensor allocation and full characterization 真实处理器的热监测:传感器分配和全面表征技术

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837291

Abdullah Nazma Nowroz, Ryan Cochran, S. Reda

{"title":"Thermal monitoring of real processors: Techniques for sensor allocation and full characterization","authors":"Abdullah Nazma Nowroz, Ryan Cochran, S. Reda","doi":"10.1145/1837274.1837291","DOIUrl":"https://doi.org/10.1145/1837274.1837291","url":null,"abstract":"The increased power densities of multi-core processors and the variations within and across workloads lead to runtime thermal hot spots locations of which change across time and space. Thermal hot spots increase leakage, deteriorate timing, and reduce the mean time to failure. To manage runtime thermal variations, circuit designers embed within-die thermal sensors that acquire temperatures at few selected locations. The acquired temperatures are then used to guide runtime thermal management techniques. The capabilities of these techniques are essentially bounded by the spatial thermal resolution of the sensor measurements. In this paper we characterize temperature signals of real processors and demonstrate that on-chip thermal gradients lead to sparse signals in the frequency domain. We exploit this observation to (1) devise thermal sensor allocation techniques, and (2) devise signal reconstruction techniques that fully characterize the thermal status of the processor using the limited number of measurements from the thermal sensors. To verify the accuracy of our methods, we compare our temperature characterization results against thermal measurements acquired from a state-of-the-art infrared camera that captures the mid-band infrared emissions from the back of the die of a 45 nm dual-core processor. Our results show that our techniques are capable of accurately characterizing the temperatures of real processors.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"73 1","pages":"56-61"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80544236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 82

Reliability aware power management for dual-processor real-time embedded systems 基于可靠性的双处理器实时嵌入式系统电源管理

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837480

R. Sridharan, R. Mahapatra

{"title":"Reliability aware power management for dual-processor real-time embedded systems","authors":"R. Sridharan, R. Mahapatra","doi":"10.1145/1837274.1837480","DOIUrl":"https://doi.org/10.1145/1837274.1837480","url":null,"abstract":"Primary-Backup (PB) model has been a widely used model for reliability in dual-processor real-time systems. In recent literature, there have been a few works focussing on minimizing energy consumption of periodic task sets executing on such systems. One of the major drawbacks of these works is that they ignore the effects of frequency-scaling on fault arrival rates. In this paper, we present a modified Primary-Backup model for dual-processor systems that aims to maintain the reliability when employing power management techniques to minimize the overall energy consumption. Furthermore, the proposed approach exploits the uncertainties in the execution time of real-time tasks to better predict the available slack for energy management. The proposed modified PB-based Reliability-Aware Power Management (RAPM) approach was tested with synthetic task sets on both homogeneous and heterogeneous dual-processor systems. Simulation results show that it can achieve up to 67 % savings in expected energy consumption for low utilization task sets and up to 32 % savings for high utilization task sets without any loss in reliability in heterogeneous dual-processor systems.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"21 1","pages":"819-824"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90456125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

3-D stacked die: Now or future? 3-D叠模:现在还是未来?

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837350

S. Bansal, J. Rey, A. Yang, Myung-Soo Jang, L. C. Lu, P. Magarshack, P. Marchal, R. Radojcic

引用次数: 2

Multi-threaded collision-aware global routing with bounded-length maze routing 具有有界长度迷宫路由的多线程冲突感知全局路由

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837324

Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao

{"title":"Multi-threaded collision-aware global routing with bounded-length maze routing","authors":"Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao","doi":"10.1145/1837274.1837324","DOIUrl":"https://doi.org/10.1145/1837274.1837324","url":null,"abstract":"Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, which adopts a heuristic-BLMR, identifies less-wirelength routing results with less runtime than state-of-the-art global routers. This study also proposes a parallel multi-threaded collision-aware global router based on a previous sequential global router. Unlike the conventional partition-based concurrency strategy, the proposed algorithm uses a task-based concurrency strategy. Experimental results reveal that the proposed sequential global router uses less wirelength and runs about 1.9X to 18.67X faster than other state-of-the-art global routers. Compared to the proposed sequential global router, the proposed parallel global router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route benchmarks, respectively, when running on an Intel quad-core system.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"42 1","pages":"200-205"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86683757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 74

Electronic design automation for social networks 社交网络的电子设计自动化

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837429

A. DeOrio, V. Bertacco

引用次数: 1

Cost-aware three-dimensional (3D) many-core multiprocessor design 具有成本意识的三维(3D)多核多处理器设计

Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837308

Jishen Zhao, Xiangyu Dong, Yuan Xie

引用次数: 32