2022 IEEE International Solid- State Circuits Conference (ISSCC)最新文献_第8页

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS 5GS/s 360MHz-BW 68dB-DR连续时间1-1-1滤波MASH ΔΣ 40nm CMOS ADC

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731789

Qilong Liu, L. Breems, Chenming Zhang, Shagun Bajoria, M. Bolatkale, R. Rutten, G. Radulov

{"title":"A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS","authors":"Qilong Liu, L. Breems, Chenming Zhang, Shagun Bajoria, M. Bolatkale, R. Rutten, G. Radulov","doi":"10.1109/ISSCC42614.2022.9731789","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731789","url":null,"abstract":"In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1]–[3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to layout parasitics due to the high sampling rates, and most important of all, are power hungry, consuming several hundreds of mW. In this paper, we propose a filtering rnulti-stage noise-shaping (MASH) ΔΣ ADC architecture that overcomes the abovementioned drawbacks. Passive delay compensating filters [4] are used to realize broadband and deep suppression of the input signal component at the internal filter nodes of the ADC. As a result, no interstage DACs are needed, which are commonly required to generate the quantization error replicas in a MASH ΔΣ ADC, saving substantial power and greatly reducing the parasitic load of the high-speed critical nodes. Moreover, because of the absence of signal content at the internal filter nodes, the backend stages of the MASH architecture have relaxed linearity requirements and can be implemented with simple low-power Gm-C filters. Precise excess loop delay and excess phase compensation are accomplished with a partly resistive and capacitive stabilization DAC, enabling very-high-speed operation of the ΔΣ loops. The realized MASH ADC is sampled at 5GHz and achieves 68dB/65dB DR/peak SNDR over a 360MHz bandwidth, -78dBc THD at -1dBFS for a 115MHz input signal, and consumes 158mW. Implemented in a mature 40nm CMOS technology, the ADC occupies only 0.21 mm2 core area, achieves 2× lower power, 5dB higher Schreier FOM and 2× lower Walden FOM compared to state-of-the-art broadband CT ADCs in advanced 16nm-28nm nodes [1]–[3].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"66 1","pages":"414-416"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81068519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur 级联锁相环(LC-PLL + RO-PLL)，具有可编程双调整功能，实现204fs集成抖动(100kHz至100MHz)和-72dB参考杂散

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731676

Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Yaopei Chang, Chih-Hsien Chang, R. Staszewski

{"title":"A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur","authors":"Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Yaopei Chang, Chih-Hsien Chang, R. Staszewski","doi":"10.1109/ISSCC42614.2022.9731676","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731676","url":null,"abstract":"Many PLLs, including those used for mm-wave 5G communications, require deep-sub-picosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a recent trend in addressing this problem [2]–[4]. They are composed of two stages: the 1st stage (PLL #1) receives an external frequency reference FREF to generate a filtered reference of several GHz feeding into the 2nd stage (PLL #2) that features a lower division ratio and a wide bandwidth for better overall jitter performance. Although the cascaded PLL can chose from various combinations of oscillators, e.g., LC-tank and ring-oscillator (RO), the PLL #2 using an RO can benefit from a small size, easy integration, wide frequency-tuning range (FTR), and multiphase clock outputs (e.g., for directly supporting multibeam antenna arrays). Normally, the RO-PLL cannot achieve the same jitter performance as an LC-PLL, but here a low value of $N$ in the wide-bandwidth integer-N configuration of PLL #2 makes this distinction less relevant.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"963 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80316030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core Zen3: AMD第二代7nm x86-64微处理器核心

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731678

T. Burd, Wilson Li, James Pistole, S. Venkataraman, M. McCabe, Timothy Johnson, J. Vinh, Thomas Yiu, M. Wasio, H. Wong, Daryl Lieu, Jonathan White, B. Munger, Joshua Lindner, Javin Olson, S. Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar

{"title":"Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core","authors":"T. Burd, Wilson Li, James Pistole, S. Venkataraman, M. McCabe, Timothy Johnson, J. Vinh, Thomas Yiu, M. Wasio, H. Wong, Daryl Lieu, Jonathan White, B. Munger, Joshua Lindner, Javin Olson, S. Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar","doi":"10.1109/ISSCC42614.2022.9731678","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731678","url":null,"abstract":"“Zen 3” is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation “Zen 2” core [1], as well as the same platform infrastructure, the primary “Zen 3” design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency. The core complex unit (CCX) consists of 8 “Zen 3” cores, each with a 0.5MB private L2 cache, and a 32MB shared L3 cache. Increasing this from 4 cores and 16MB L3 in the prior generation provides additional performance uplift, in addition to the IPC and frequency improvements. The “Zen 3” CCX shown in Fig. 2.7.1 contains 4.08B transistors in 68mm2, and is used across a broad array of client, server, and embedded market segments.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"150 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79449759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An SpO2 Sensor Using Reconstruction-Free Sparse Sampling for 70% System Power Reduction 基于无重构稀疏采样的SpO2传感器系统功耗降低70%

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731113

Sina Faraji Alamouti, Cem Yalcin, Jasmine Jan, Jonathan Ting, A. Arias, R. Muller

{"title":"An SpO2 Sensor Using Reconstruction-Free Sparse Sampling for 70% System Power Reduction","authors":"Sina Faraji Alamouti, Cem Yalcin, Jasmine Jan, Jonathan Ting, A. Arias, R. Muller","doi":"10.1109/ISSCC42614.2022.9731113","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731113","url":null,"abstract":"Low arterial blood oxygenation (SpO2) is a measure of hypoxemia and a sign of problems relating to breathing and circulation. Progressive drop in arterial SpO2 can be an early indicator of severe disease in COVID-19 patients [1]. A hypoxic state can occur rapidly and without a patient's knowledge; therefore, early detection of SpO2 decline can be lifesaving. In other respiratory system diseases such as COPD and sleep apnea, continuously monitoring of SpO2 with a pulse oximeter can enable timely diagnosis of oxygen desaturation. SpO2 is measured with Photoplethysmography (PPG) that uses a photodetector (PD) to detect either the transmission or reflection of light from the surface of the skin at two different light wavelengths. Commercial fingertip SpO2 sensors are not designed for chronic wear and require user intervention to trigger measurements. Alternatively, wearable SpO2 recording devices in the form of watches and rings can operate in the background with minimal user intervention. However, continuous acquisition of SpO2 can present a significant power burden to a wearable device since high-power LEDs must be powered on for each sample, dominating the power dissipation of the sensor. We present a low-power pulse oximeter sensor IC that utilizes sparse sampling to reduce the overall power by 70%.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"44 1","pages":"344-346"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78955280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance 一种带时间放大相频检测器的25.8GHz整数n锁相环，具有60fsrms的抖动，-252.8dB的FoMJ和稳健的锁捕获性能

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731578

Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang

引用次数: 15

A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS 2.29pJ/b 112Gb/s有线收发器，RX 4-Tap FFE，用于28nm CMOS中远应用

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731591

Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, S. Jia, Congcong Chen, Jiaqi Yu

{"title":"A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS","authors":"Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, S. Jia, Congcong Chen, Jiaqi Yu","doi":"10.1109/ISSCC42614.2022.9731591","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731591","url":null,"abstract":"The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1st-tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"40 1","pages":"118-120"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73571719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump 一种480倍倍的13.2- 17.3 ghz子采样锁相环，采用比例分电荷泵实现6.6mW功率和-248.1 dB FoM

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731760

Luya Zhang, A. Niknejad

引用次数: 5

Session 2 Overview: Processors 第二部分概述:处理器

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/isscc42614.2022.9731559

引用次数: 0

SE4: The Bright and Dark Side of Artificial Intelligence (AI) SE4:人工智能的光明与黑暗

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/isscc42614.2022.9731570

引用次数: 0

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization 具有TSV自动校准方案和基于机器学习的布局优化的192gb 12-High 896 gb /s HBM3 DRAM

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI: 10.1109/ISSCC42614.2022.9731562

Myeong-Jae Park, H. Cho, T. Yun, S. Byeon, Young Jun Koo, Sang-Sic Yoon, Dong-Uk Lee, Seokwoo Choi, Ji Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, B. Yoon, Y. Park, Sangmuk Oh, C. Lee, Tae-Kyun Kim, S. Lee, Hyunwoo Kim, Yucheon Ju, SeungGyeon Lim, S. Baek, Kyo Yun Lee, Sang Hun Lee, Woodward We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seungtaek Yang, Gunho Lee, In-Keun Kim, Y. Jeon, Jaewon Park, J. Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, T. Hwang, Junghyun Shin, Yu-Ri Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, J. Chun, Joohwan Cho

{"title":"A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization","authors":"Myeong-Jae Park, H. Cho, T. Yun, S. Byeon, Young Jun Koo, Sang-Sic Yoon, Dong-Uk Lee, Seokwoo Choi, Ji Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, B. Yoon, Y. Park, Sangmuk Oh, C. Lee, Tae-Kyun Kim, S. Lee, Hyunwoo Kim, Yucheon Ju, SeungGyeon Lim, S. Baek, Kyo Yun Lee, Sang Hun Lee, Woodward We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seungtaek Yang, Gunho Lee, In-Keun Kim, Y. Jeon, Jaewon Park, J. Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, T. Hwang, Junghyun Shin, Yu-Ri Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, J. Chun, Joohwan Cho","doi":"10.1109/ISSCC42614.2022.9731562","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731562","url":null,"abstract":"Ever since the introduction of high bandwidth memory (HBM DRAM) and its succeeding line-ups, HBM DRAM has been heralded as a prominent solution to tackle the memory wall problem. However, despite continual memory advancements the advent of high-end systems, including supercomputers, hyper-scale data centers and machine learning accelerators, are expediting requirements for higher-performance memory solutions. To accommodate the increasing system-level demands, we introduce HBM3 DRAM, which employs multiple new features and design schemes. Techniques such as an on-die ECC engine, internal NN-DFE I/O signaling, TSV auto-calibration, and layout optimization based on machine-learning algorithms are implemented to efficiently control timing skew margins and SI degradation trade-offs. Furthermore, reduced voltage swings allow for improved memory bandwidth, density, power efficiency and reliability.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"15 1","pages":"444-446"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86049175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16