A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI:10.1109/ISSCC42614.2022.9731110

Jonghak Yuh, Jason Li, Heguang Li, Y. Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, S. Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex S. Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, J. Sohn, H. Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, I. V., C. G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, F. Moogat, In-Soo Yoon, K. Kanda, Takahiro Shimizu, N. Shibata, Takashi Shigeoka, K. Yanagidaira, T. Kodama, R. Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe

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引用次数: 8

Abstract

The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm2 which is 8.7% higher than prior work [1]. High-performance is the key enabler for 4b/cell NAND Flash to enter mainstream systems. This work delivers a 60MB/s programming throughput and a 65μs tR with an 8kB central WL stair architecture and contact-through-WL (CTW) region. 2.4Gb/s I/O speed is achieved with LTT and CTT combo drivers. A 45% reduction in the read and write data transfer energy is achieved by employing VCCQ domain design. A time-division peak-power-management (TD-PPM) feature effectively reduces system peak power while maximizing system performance. Cache DFT and I/O DFT functions enable a high-speed testing methodology at wafer level. These features are summarized and compared to previously reported 4b/cell Flash memories in Fig. 7.1.1.

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一个1tb 4b/Cell 4-Plane 162层3D闪存，带有2.4 gb /s I/O速度接口

所提出的1Tb 4b/cell 162 WL层3D闪存实现了15gb /mm2的面密度，比之前的工作提高了8.7%[1]。高性能是4b/cell NAND闪存进入主流系统的关键因素。这项工作提供了60MB/s的编程吞吐量和65μs的tR，具有8kB的中央WL楼梯结构和接触式穿过WL (CTW)区域。使用LTT和CTT组合驱动程序可实现2.4Gb/s的I/O速度。通过采用VCCQ域设计，实现了读写数据传输能量降低45%。时分峰值功率管理(TD-PPM)特性有效地降低系统峰值功率，同时最大限度地提高系统性能。缓存DFT和I/O DFT功能实现了晶圆级的高速测试方法。图7.1.1总结了这些特征，并与先前报道的4b/cell闪存进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 IEEE International Solid- State Circuits Conference (ISSCC)

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