1- 18ghz分布式堆叠互补三平衡无源混频器,具有高达33dBm IIP3和集成LO驱动器,采用45nm CMOS SOI

C. Hill, J. Buckwalter
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引用次数: 2

摘要

如图19.7.1所示,大规模MIMO或数字波束形成收发器系统为多频段、多用户和联合通信与传感平台提供了灵活性。然而,宽带MIMO应用增加了冲击每个通道的期望或干扰信号的数量,从而在发射和接收RF路径中产生更高的输入功率压缩$(\ mathm {P}_{1\text{dB}})$或三阶输入拦截点(IIP3)线性要求。在高性能商用和国防无线电中,由于LNA输出通常会压缩混频器,CMOS混频器对接收器线性度造成了严重限制,导致最近在CMOS中采用混频器优先的方法来提高接收器线性度[1]。当需要高度线性的微波混频器时,IIIV工艺,如GaAs,是Schottky二极管的首选,它提供较低的$\ mathm {R}_{\text{on}}}\ mathm {C}_{\text{off}}$和高势垒电压。商用GaAs混频器提供超过30dBm的IIP3s。然而,III-V混频器通常为驱动放大器使用一个单独的过程,导致多个芯片具有高驱动功耗(通常超过1W),以在宽的LO频率范围内提供所需的15至30dbm LO功率[2]。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI
Massive MIMO or digital-beamforming transceiver systems, shown in Fig. 19.7.1, offer flexibility for multiband, multi-user, and joint communication-and-sensing platforms. However, wideband MIMO applications increase the number of desired or interfering signals that impinge on each channel, creating higher input-power-compression $(\mathrm{P}_{1\text{dB}})$ or 3rd-order input-intercept-point (IIP3) linearity requirements in both the transmitting and receiving RF paths. In high-performance commercial and defense radios, CMOS mixers place critical limitations on receiver linearity as the LNA output typically compresses the mixer, leading to recent work on mixer-first approaches in CMOS to improve receiver linearity [1]. When highly linear microwave mixers are demanded, IIIV processes, such as GaAs, are favored for Schottky diodes, which offer lower $\mathrm{R}_{\text{on}}\mathrm{C}_{\text{off}}$ and high barrier voltages. Commercially available GaAs mixers offer IIP3s exceeding 30dBm. However, III-V mixers typically use a separate process for the driver amplifier, resulting in multiple chips with high driver power consumption (typically exceeding 1W) to deliver the required 15-to-30dBm LO power across a broad LO frequency range [2].
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