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2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)最新文献

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Modeling of Buck Converter with 3D Air-Core Inductor 带三维空芯电感的Buck变换器建模
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229676
Hesheng Lin, G. van der Plas, Xiao Sun, D. Velenis, E. Beyne, R. Lauwereins
{"title":"Modeling of Buck Converter with 3D Air-Core Inductor","authors":"Hesheng Lin, G. van der Plas, Xiao Sun, D. Velenis, E. Beyne, R. Lauwereins","doi":"10.1109/ESTC48849.2020.9229676","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229676","url":null,"abstract":"A high-efficiency and high-power density buck converter is presented in this work with in-package 3D air-core inductor (150 µm thick). To optimize the system efficiency at targeted power density, an analytical model for both the 3D inductor and power switches is developed. Compared to 3D EM simulation, the proposed inductor model has maximum modeling error of 12% and 25% for the inductance and resistance calculations respectively. With the proposed design methodology, an inductor Q factor up to 35 @ 300 MHz is achieved. 1/2-ratio buck converter can reach 90% efficiency @ 1–5W/mm2 based on three optimized inductor designs, with VOUT ranging from 0.7 V to 0.9 V and based on 28 nm CMOS.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"14 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87779036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Tooling and procedures for hybrid integration of lasers by flip-chip technology 用倒装芯片技术混合集成激光器的工具和程序
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229661
C. Mitchell, Ke Li, Ralph Schachler, A. Khokhar, Xia Chen, S. Stankovic, Xiangjun Wang, N. Sessions, K. Grabska, D. Thomson, Christoph Daedlow, G. Reed, J. Wilkinson
{"title":"Tooling and procedures for hybrid integration of lasers by flip-chip technology","authors":"C. Mitchell, Ke Li, Ralph Schachler, A. Khokhar, Xia Chen, S. Stankovic, Xiangjun Wang, N. Sessions, K. Grabska, D. Thomson, Christoph Daedlow, G. Reed, J. Wilkinson","doi":"10.1109/ESTC48849.2020.9229661","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229661","url":null,"abstract":"A method of achieving hybrid integration of laser bars on a silicon platform, using chip-flip bonding, is presented. A support structure etched into the substrate is used to provide vertical alignment to the plane utilizing a gimballed placement laser tool. In-plane accuracy is provided by bonder tolerances, with facet-to-facet alignment enabled by high magnification optics and the dimensions of the laser bar. Chip design features have increased allowed tolerances during fabrication of the support structure giving a route to higher yield in manufacture.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"12 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86895063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Research On FOPLP Package of multi-chip Power Module 多芯片电源模块FOPLP封装研究
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229816
Jing Jiang, J. Huo, Guangdong Song, H. Ye, Debo Liu, Guoqi Zhang, Jun Tao Jun Wang
{"title":"Research On FOPLP Package of multi-chip Power Module","authors":"Jing Jiang, J. Huo, Guangdong Song, H. Ye, Debo Liu, Guoqi Zhang, Jun Tao Jun Wang","doi":"10.1109/ESTC48849.2020.9229816","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229816","url":null,"abstract":"Power devices are developing for the small volume, high performance and modularization. With more and more application scenarios of Brushless Direct Current Motor (BLDC), MOSFET multi-chip module (MCM) is popular with people. However, the conventional wire Bonding and Copper clip welding technology struggles to meet the requirements for the excessive heat accumulation and complex logic problems in MCM. While the above problems can be well solved by using the new Fan out panel level packing(FOPLP) technology for QFN packaging of multi-chip. The traditional welding technology is used at the bottom of the chip, and the copper porous link is used at the top of the chip with low parasitic capacitance, inductance and low Rdson in electrical performance. In respect to thermal management, the θJC on the top of the chip can be reduced, which has the effect of double-sided heat dissipation. Top Layer interconnection technology is adopted in the packaging scheme, which can have complex circuit layout.This paper mainly describes the technical implementation of this packaging technology, adopting the finite element software to establish a three-dimensional model of a new type of FOPLP and wire welding packaging for MCM. The thermal resistance of different packaging schemes is calculated to confirm the advantages and disadvantages of different schemes by the way of thermal simulation, the internal temperature distribution of different packaging structures and the main influencing factors of the thermal resistance of packaging compared.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"19 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91135898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ESTC 2020 Future Events Page ESTC 2020未来活动页面
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/estc48849.2020.9229718
{"title":"ESTC 2020 Future Events Page","authors":"","doi":"10.1109/estc48849.2020.9229718","DOIUrl":"https://doi.org/10.1109/estc48849.2020.9229718","url":null,"abstract":"","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"50 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91213193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Brick or Tile? Evaluation of Integration Concepts for Microwave Phased Array Antennas 砖还是瓦?微波相控阵天线集成概念的评价
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229703
P. Uhlig, A. Friedrich, U. Lewark, O. Litschke
{"title":"Brick or Tile? Evaluation of Integration Concepts for Microwave Phased Array Antennas","authors":"P. Uhlig, A. Friedrich, U. Lewark, O. Litschke","doi":"10.1109/ESTC48849.2020.9229703","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229703","url":null,"abstract":"This paper will present examples of two different approaches to the packaging of AESAs: Brick, where the active circuits are perpendicular to the antenna array and Tile with the active circuitry in plane with the antenna elements. For both concepts solutions are discussed to enable feed-networks for 30 GHz together with multi-technology integration of GaN/GaAs circuits for Tx and Rx together with highly integrated SiGe technology for phase and amplitude steering. The requirements for microwave signal distribution, power supply and thermal management of the active components shall be explained and demonstrated as concept and in hardware.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90290623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
LTCC Embedding of SiC Power Devices for High Temperature Applications over 400 °C 用于400°C以上高温应用的SiC功率器件的LTCC嵌入
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229859
B. Bayer, M. Groccia, Hoang Linh Bach, Christoph Friedrich Bayer, A. Schletz, C. Lenz, S. Ziesche
{"title":"LTCC Embedding of SiC Power Devices for High Temperature Applications over 400 °C","authors":"B. Bayer, M. Groccia, Hoang Linh Bach, Christoph Friedrich Bayer, A. Schletz, C. Lenz, S. Ziesche","doi":"10.1109/ESTC48849.2020.9229859","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229859","url":null,"abstract":"This paper encompasses a novel packaging concept based on the embedding of semiconductor devices in Low Temperature Cofired Ceramic (LTCC) multilayer substrates. The wide-bandgap power semiconductor made out of silicon carbide (SiC) is embedded within the co-firing process of the LTCC at around 750 to 850 °C. Filled vias and inlays, realized in the same process, form the electrical interconnection and heat dissipation. This approach combines high-temperature stability over 400 °C junction temperature, compactness, and 3D integration ability into one concept to fulfill all advantages of SiC power semiconductors and other future wide bandgap devices. Moreover, the package design aims for hermetical sealing and harsh environment applications. Various geometric concepts for LTCC pre-packages are developed to investigate the thermal behavior. Two of the ideas could improve the thermal resistance up to 45 % compared to the state of the art power modules. Afterward, complete power modules were designed. In the end, electrical simulations have been executed to analyze the parasitic inductances and the different concepts are discussed.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"8 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89731433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reliability Impact of Assembly Materials for Micro-BGA Components in High Reliability Applications 高可靠性应用中微型bga组件装配材料对可靠性的影响
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229828
S. Stoyanov, C. Bailey, P. Stewart, Graeme Morrison
{"title":"Reliability Impact of Assembly Materials for Micro-BGA Components in High Reliability Applications","authors":"S. Stoyanov, C. Bailey, P. Stewart, Graeme Morrison","doi":"10.1109/ESTC48849.2020.9229828","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229828","url":null,"abstract":"Electronics manufacturers of high-reliability and harsh environment equipment rely increasingly on the adoption of electronics packages from the commercial market supply chain. Chip Scale Packages (CSP) such as micro-ball grid arrays (μBGAs) provide a range of IC functions available in the format of very small size package architectures and increasingly at lower cost. To meet the stringent reliability requirements posed by such applications, stress-reducing designs, and assembly materials for μBGAs must be developed and optimised. This paper details the results from reliability tests assessing the fatigue life of μBGA solder joints for several package-board assembly configurations. Assemblies based on rigid and compliant printed circuit boards (PCBs) are discussed as well as the impact of edgebond and underfill materials on the solder joint reliability. A physics-of-failure modelling approach for assessing the reliability performance of the μBGA assemblies is developed and demonstrated. Results from the thermo-mechanical simulations were validated and the models were used to predict and explain the solder joints’ physics-of-failure. The use of the modelling and experimental data for development of μBGA lifetime model is also presented and discussed.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"31 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89177952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Study of Cu-Sn-In system for low temperature, wafer level solid liquid inter-diffusion bonding Cu-Sn-In体系低温晶片级固液互扩散键合的研究
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229696
J. Hotchkiss, V. Vuorinen, Hongqun Dong, G. Ross, J. Kaaos, M. Paulasto-Kröckel, T. Wernicke, A. Pönninger
{"title":"Study of Cu-Sn-In system for low temperature, wafer level solid liquid inter-diffusion bonding","authors":"J. Hotchkiss, V. Vuorinen, Hongqun Dong, G. Ross, J. Kaaos, M. Paulasto-Kröckel, T. Wernicke, A. Pönninger","doi":"10.1109/ESTC48849.2020.9229696","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229696","url":null,"abstract":"The Solid Liquid Interdiffusion (SLID) bonds carried out for this work take advantage of the Cu-In-Sn ternary system to achieve low temperature wafer-level bonds. The experiments were carried out across a range of temperatures and the results cover optimized wafer-level bonding process, the formation of the bond microstructure, mechanical performance, as well as the effects of thermal aging.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"86 10","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91549009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Layer Transfer Process Development For SiGe Based Microbolometer Integration 基于SiGe的微热计集成的层转移工艺开发
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229812
C. Kaynak, A. Goeritz, Patrick Krueger, T. Voß, Y. Yamamoto, P. Heinrich, U. Saarow, M. Wietstruck, M. Kaynak
{"title":"Layer Transfer Process Development For SiGe Based Microbolometer Integration","authors":"C. Kaynak, A. Goeritz, Patrick Krueger, T. Voß, Y. Yamamoto, P. Heinrich, U. Saarow, M. Wietstruck, M. Kaynak","doi":"10.1109/ESTC48849.2020.9229812","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229812","url":null,"abstract":"This paper presents the transfer of the SiGe multi quantum well (MQW) layer stack on top of a CMOS wafer for the integration of a microbolometer device. Due to the limitations of a thermal budget for the post processing of a CMOS wafer, a full layer transfer of high temperature grown (>600 C) SiGe layers stack is transferred on BiCMOS wafer on 200 mm wafer level. The full process flow of the layer transfer based on oxide-oxide fusion bonding and the critical process steps for surface conditions of the wafers in terms of roughness and the edge trimming process before the final grinding are detailed. After the optimization of those process steps, a successful full layer transfer of the SiGe MQW layers on top of a BiCMOS wafer is demonstrated by the realization of a SiGe MQW based microbolometers.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"26 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82627303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of Etching SIC VIAS for High Power Elctronics and Harsh Enviornment Mems 大功率电子及恶劣环境微机电系统SIC过孔刻蚀研究
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC) Pub Date : 2020-09-15 DOI: 10.1109/ESTC48849.2020.9229659
P. Mackowiak, K. Erbacher, M. Schiffer, H. Ngo, M. Schneider-Ramelow, K. Lang
{"title":"Investigation of Etching SIC VIAS for High Power Elctronics and Harsh Enviornment Mems","authors":"P. Mackowiak, K. Erbacher, M. Schiffer, H. Ngo, M. Schneider-Ramelow, K. Lang","doi":"10.1109/ESTC48849.2020.9229659","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229659","url":null,"abstract":"This paper describes the research on the process development and process optimization of via etching of silicon carbide using reactive ion etching. The experiments were performed using a design of experiments (DOE) with a total 26 experiments and D-efficiency of over 85.4 finding the most significant process parameters impacting the etch result. Optimizing the process we could achieve etch depth of 200µm with an etch rate of up to 2µm/min. The ability of etching SiC with a high etch rate enables new application for harsh environments micro electromechanical systems (MEMS) and high power electronics.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"6 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82965221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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