Hesheng Lin, G. van der Plas, Xiao Sun, D. Velenis, E. Beyne, R. Lauwereins
{"title":"Modeling of Buck Converter with 3D Air-Core Inductor","authors":"Hesheng Lin, G. van der Plas, Xiao Sun, D. Velenis, E. Beyne, R. Lauwereins","doi":"10.1109/ESTC48849.2020.9229676","DOIUrl":null,"url":null,"abstract":"A high-efficiency and high-power density buck converter is presented in this work with in-package 3D air-core inductor (150 µm thick). To optimize the system efficiency at targeted power density, an analytical model for both the 3D inductor and power switches is developed. Compared to 3D EM simulation, the proposed inductor model has maximum modeling error of 12% and 25% for the inductance and resistance calculations respectively. With the proposed design methodology, an inductor Q factor up to 35 @ 300 MHz is achieved. 1/2-ratio buck converter can reach 90% efficiency @ 1–5W/mm2 based on three optimized inductor designs, with VOUT ranging from 0.7 V to 0.9 V and based on 28 nm CMOS.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"14 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTC48849.2020.9229676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A high-efficiency and high-power density buck converter is presented in this work with in-package 3D air-core inductor (150 µm thick). To optimize the system efficiency at targeted power density, an analytical model for both the 3D inductor and power switches is developed. Compared to 3D EM simulation, the proposed inductor model has maximum modeling error of 12% and 25% for the inductance and resistance calculations respectively. With the proposed design methodology, an inductor Q factor up to 35 @ 300 MHz is achieved. 1/2-ratio buck converter can reach 90% efficiency @ 1–5W/mm2 based on three optimized inductor designs, with VOUT ranging from 0.7 V to 0.9 V and based on 28 nm CMOS.