2019 IEEE 69th Electronic Components and Technology Conference (ECTC)最新文献_第3页

Electrochemical Impedance Spectroscopy (EIS) for Monitoring the Water Load on PCBAs Under Cycling Condensing Conditions to Predict Electrochemical Migration Under DC Loads 电化学阻抗谱(EIS)监测循环冷凝条件下pcba的水负荷以预测直流负载下的电化学迁移

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00084

S. Lauser, T. Richter, Verdingovas Vadimas, R. Ambat

{"title":"Electrochemical Impedance Spectroscopy (EIS) for Monitoring the Water Load on PCBAs Under Cycling Condensing Conditions to Predict Electrochemical Migration Under DC Loads","authors":"S. Lauser, T. Richter, Verdingovas Vadimas, R. Ambat","doi":"10.1109/ECTC.2019.00084","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00084","url":null,"abstract":"Humidity induced failures like metallic dendrite formation are a major problem for automotive electronic components. The harsh environment, where operating conditions in terms of temperature and humidity vary, can repeatedly provoke thin water layers on the surface of Printed Circuit Board Assemblies (PCBAs). The presence of a water film on electronics enables various corrosive processes. The understanding of the film formation and its effects is therefore crucial for assessing the humidity robustness of a specific setup. In this work, we conducted temperature and humidity load experiments with test boards containing interdigitated copper traces of different gap sizes on FR-4 substrate material. We repeatedly provoked condensation and evaporation conditions on the boards' surfaces by temperature cycling between 25 °C and 55 °C at 97 %rH. Electrochemical impedance spectroscopy (EIS) was employed as testing approach to detect the water film formation and respectively its evaporation. An AC excitation of 10 mV over a frequency range between 1 kHz and 100 kHz was used. Simultaneously, the commonly used SIR (Surface Insulation Resistance) test method was conducted at 5 V DC. This method lacks in delivering information on the actual water layer build up, but it detects the growth of dendrites, for which the DC voltage is required. The evaluated results of the EIS testing show, that the magnitude of water present can be depicted by the change in phase shift in the high frequency domain. We could also detect the water film closing for different gap sizes upon condensation. The DC measurements showed a correlation in terms of dendrite formation upon certain water load conditions.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"41 1","pages":"515-521"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84833907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Integration and Characterization of InP Die on Silicon Interconnect Fabric 硅互连结构上InP模的集成与表征

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00088

E. Sorensen, Boris Vaisband, SivaChandra Jangam, T. Shirley, S. Iyer

{"title":"Integration and Characterization of InP Die on Silicon Interconnect Fabric","authors":"E. Sorensen, Boris Vaisband, SivaChandra Jangam, T. Shirley, S. Iyer","doi":"10.1109/ECTC.2019.00088","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00088","url":null,"abstract":"The silicon interconnect fabric (Si-IF) is a wafer-level packaging platform that enables heterogeneous integration of die at ultra-fine pitch (2 to 10 µm) directly onto a lithographically defined silicon wafer with no intermediate packaging hierarchy. The die are attached with an extremely tight inter-dielet spacing (< 100 µm). The small inter-dielet spacing is especially advantageous in high frequency applications due to reduced loss associated with the transmission line behavior of off-chip interconnects. Since indium phosphide (InP) is a popular technology choice for high frequency applications, the goal of this paper is to investigate the efficacy of direct Au-Au thermo-compression bonding (TCB) of InP die to the Si-IF platform for the first time. To evaluate this process, 84 InP die were successfully bonded to the Si-IF. The sheer strength of the integrated die ranges from 38 MPa to 238 MPa, for die that were attached using pressure ranging, respectively, from 100 MPa to 350 MPa. Daisy chain resistance of the bonded die was measured exhibiting good correlation with calculated theoretical values. After thermal cycling, it was found that 100% of the attached die withstood all thermal stressing despite the thermal mismatch of 2 ppm/K between the die and the Si-IF.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"543-549"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80341226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Cu-Cu Bonding by Low-Temperature Sintering of Self-Healable Cu Nanoparticles 低温烧结自愈纳米铜的Cu-Cu键合研究

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00105

Junjie Li, Qi Liang, Chen Chen, T. Shi, G. Liao, Zirong Tang

{"title":"Cu-Cu Bonding by Low-Temperature Sintering of Self-Healable Cu Nanoparticles","authors":"Junjie Li, Qi Liang, Chen Chen, T. Shi, G. Liao, Zirong Tang","doi":"10.1109/ECTC.2019.00105","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00105","url":null,"abstract":"The Cu-Cu bonding temperature by using Cu nanoparticles is mainly influenced by the size and the purity of Cu nanoparticles. To remove the oxides of Cu, reducing atmosphere is always introduced into the sintering and bonding process. In this paper, a new Cu-Cu bonding method by sintering of self-healable Cu nanoparticles was proposed. With this method, the surface oxidation layer of Cu nanoparticle can be removed without reducing atmosphere at sintering and bonding process. In order to research the self-healing properties of the surface oxidized Cu nanoparticles, the sintering and bonding experiments were carried out under an Ar atmosphere. With self-healable Cu nanoparticles, the electrical resistivity of sintered Cu film can be reduced to lower than 5 µΩ·cm after sintering, and a high shear strength Cu-Cu joint over 25 MPa can be achieved after bonding at 250 °C. The oxygen content was also significantly reduced during the sintering and bonding process, which reflected the excellent self-healing property of Cu nanoparticle paste. The high Cu-Cu bonding strength and no requirement for reducing atmosphere indicate that the proposed self-healable Cu nanoparticle paste is promising to be wildly used in advanced electronics packaging.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"65 1","pages":"661-666"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90863091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Reduction of Ag Corrosion Rate During Decapsulation of Ag Wire Bond Packages 银焊丝包解封装过程中银腐蚀速率的降低

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00325

Young-Ja Kim, Jinho Hah, K. Moon, C. Wong

引用次数: 1

A High-Bandwidth Fine-Pitch 2.57Tbps/mm In-package Communication Link Achieving 48fJ/bit/mm Efficiency 实现48fJ/bit/mm效率的高带宽细间距2.57Tbps/mm封装通信链路

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00107

N. Pantano, G. van der Plas, P. Bex, P. Nolmans, D. Velenis, M. Verhelst, E. Beyne

引用次数: 3

An Assessment of Electromigration in 2.5D Packaging 2.5D封装中电迁移的评估

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00-25

Jiefeng Xu, S. McCann, Huayan Wang, Jing Wang, Van-Lai Pham, S. Cain, G. Refai-Ahmed, S.B. Park

{"title":"An Assessment of Electromigration in 2.5D Packaging","authors":"Jiefeng Xu, S. McCann, Huayan Wang, Jing Wang, Van-Lai Pham, S. Cain, G. Refai-Ahmed, S.B. Park","doi":"10.1109/ECTC.2019.00-25","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-25","url":null,"abstract":"In this study, an accelerated Electromigration (EM) test was performed. The test vehicle has four types of common interconnect structure. The first one is a classic Ball Grid Array (BGA), short for BGA; the second one is a solder ball with a copper via on top, short for BGA-Via; the third one is an individual copper via in the substrate, short for Via; the last one is an individual copper Plated Through Hole (PTH), short for PTH in the substrate. The built-in serpentine copper fine lines around each structure were designed to monitor the local temperature in-situ. All test vehicles were stressed at 150oC temperature with 12A current. The voltage of each test structure and the resistance of the serpentine line were recorded in-situ. The results show that different micro-electrical structures have great effects on EM behavior, especially the time to failure (TTF). In BGA test structure, the failure occurred on the substrate side of solder ball; in BGA-Via, the failure was the depletion of the copper via. No failure was observed in Via and PTH test structures, even after an extremely long testing, although they have higher package temperature. The TTF of BGA-Via is about 2 times shorter than BGA. A finite element simulation based on Atom Flux Divergence (AFD) was performed to understand the failure mechanism and predict the TTF. The results show that via on top of solder ball will cause 10% higher current density than solder ball only. When the void underneath of the via in solder ball was nucleated, the current density will start to redistribute and reduce. In short, Via is the riskiest point for EM when it located near the solder ball.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"2150-2155"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87681776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Heterogeneous Integration of a Fan-Out Wafer-Level Packaging Based Foldable Display on Elastomeric Substrate 基于弹性基板的扇出晶圆级封装可折叠显示器的异质集成

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00048

A. Alam, A. Hanna, R. Irwin, G. Ezhilarasu, Hyunpil Boo, Yuan Hu, C. Wong, T. Fisher, S. Iyer

引用次数: 5

Compartmental EMI Shielding with Jet-Dispensed Material Technology 用喷射材料技术隔离电磁干扰屏蔽

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00119

Xuan Hong, Qizhuo Zhuo, Xinpei Cao, D. Maslyk, Noah Ekstrom, Juliet Sanchez, Selene Hernandez, Jinu Choi

引用次数: 2

Vertically Stacked and Directionally Coupled Cavity-Resonator-Integrated Grating Couplers for Integrated-Optic Beam Steering 用于集成光束导向的垂直堆叠和定向耦合腔-谐振腔-集成光栅耦合器

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00090

S. Ura, J. Inoue, K. Kintaka

{"title":"Vertically Stacked and Directionally Coupled Cavity-Resonator-Integrated Grating Couplers for Integrated-Optic Beam Steering","authors":"S. Ura, J. Inoue, K. Kintaka","doi":"10.1109/ECTC.2019.00090","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00090","url":null,"abstract":"Combination of an integrated-optic chip launching a light beam from variable position on a waveguide surface and a Fourier transform lens will provide a microoptic beam-steering device. An array of switching grating couplers in a channel waveguide is a possible candidate for varying the beam launching position with miniaturized size. Utilization of a cavity-resonator-integrated grating coupler is discussed theoretically. A resonator waveguide with a grating coupler is stacked on a bus waveguide. Vertical directional coupling between the two waveguides occurs only when a resonance wavelength coincides with that of an incident guided wave. Vertically transferred optical wave in the resonator is coupled out by the grating coupler. The vertical directional coupling can be electrically tuned by utilizing electrooptic or thermooptic effects. A design model was developed on the basis of the coupled mode analysis. Coupling characteristic of design examples using silicon waveguides were discussed. Selective coupling was predicted with the radiation efficiency of 30% and the FWHM of 1.4 x 10-3 in the effective refractive index of the cavity waveguide. Difference between neighboring peaks of radiation efficiency was predicted to be 5.2 x 10-2 indicating the resolution power of 37 for cavity length of 15 microns. These characteristics show good agreement with simulation results by the finite-difference time-domain method.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":"556-562"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75586714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems 实现未来异质集成系统的超薄晶圆混合键合

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00097

A. Phommahaxay, S. Suhard, P. Bex, S. Iacovo, J. Slabbekoorn, F. Inoue, Lan Peng, K. Kennes, E. Sleeckx, G. Beyer, E. Beyne

引用次数: 14