A High-Bandwidth Fine-Pitch 2.57Tbps/mm In-package Communication Link Achieving 48fJ/bit/mm Efficiency

Abstract

Memory bandwidth is the main bottleneck to improve the performance of today's computing systems, and the demand for bandwidth is expected to grow exponentially in the coming years. The development of advanced packaging solutions making use of a silicon bridge such as Embedded Multi-Die Interconnect Bridge (EMIB) and Fan-Out Wafer Level Package (FO-WLP) are promising solutions to achieve high bandwidth density and to bring more memory closer to the computing units. This work demonstrates a 0.3V-swing 7mm long link over a silicon bridge, running at a bitrate of 9Gbps. It achieves 48fJ/bit/mm power efficiency on 3.5um pitch wires, resulting in a bandwidth density of 2.57Tbps/mm.