2019 IEEE 69th Electronic Components and Technology Conference (ECTC)最新文献_第2页

Novel Multicore PCB and Substrate Solutions for Ultra Broadband Dual Polarized Antennas for 5G Millimeter Wave Covering 28GHz & 39GHz Range 用于覆盖28GHz和39GHz范围的5G毫米波超宽带双极化天线的新型多核PCB和基板解决方案

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00149

T. Thai, S. Dalmia, Josef Hagn, Pouya Talebbeydokhti, Yossi Tsfati

{"title":"Novel Multicore PCB and Substrate Solutions for Ultra Broadband Dual Polarized Antennas for 5G Millimeter Wave Covering 28GHz & 39GHz Range","authors":"T. Thai, S. Dalmia, Josef Hagn, Pouya Talebbeydokhti, Yossi Tsfati","doi":"10.1109/ECTC.2019.00149","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00149","url":null,"abstract":"5G millimeter wave (mmWave) communications that enables Gbps data channels often require broadband operation with dual polarization in multi frequency ranges (27-30, and 37-40GHz). Additionally, access points and base stations need large high gain antenna arrays and consistent radiation patterns across operation frequencies for ease of beam scanning control. Many stacked patch antennas were proposed as the solution. However, broadband patch antennas require thick substrate and multiple layers. For high volume production in standard substrate technology with acceptable yield, such solution targeting the consumer market has not been attempted previously. In this work, we present a novel multicore packaging approach to realize a unique and cost effective solution based on standard PCB/ Substrate technology. We demonstrate this with a complete mmWave RF module board with dimensions of 30mm x 50mm x 1.5mm. It consists of a large area dual polarization dual frequency (28GHz and 39GHz) stacked patch antenna array of 4x8 elements and fully integrated Systems-In-Package (SIPs) along with all the thermal and mechanical functions. This solution achieves a very high cross polarization discrimination ratio (>25dB), which is critical in the MIMO operation of the dual polarization network. The work includes measurements to validate the design and the packaging concept suitable for low cost mmWave 5G CPE (Customer Premises Equipment) and base station applications.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"45 1","pages":"954-959"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84767785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Assessing the Reliability of Highly Stretchable Interconnects for Flexible Hybrid Electronics 柔性混合电子器件高可拉伸互连可靠性评估

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00122

R. Sivasubramony, A. Zachariah, M. Alhendi, M. Yadav, P. Borgesen, M. Poliks, N. Stoffel, D. Shaddock, L. Yin

引用次数: 3

PowerTherm Attach Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric Using Thermocompression Bonding 利用热压键合在硅互连织物中进行电力输送和热提取的PowerTherm附加工艺

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00247

Pranav Ambhore, U. Mogera, Boris Vaisband, Ujash Shah, T. Fisher, M. Goorsky, S. Iyer

引用次数: 2

Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing Applications 高性能计算应用中亚微米信息异构集成的信号完整性

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00109

Chuei-Tang Wang, J. Hsieh, V. Chang, Shih-Ya Huang, T. Ko, H. Pu, Douglas C. H. Yu

{"title":"Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing Applications","authors":"Chuei-Tang Wang, J. Hsieh, V. Chang, Shih-Ya Huang, T. Ko, H. Pu, Douglas C. H. Yu","doi":"10.1109/ECTC.2019.00109","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00109","url":null,"abstract":"Heterogeneous integration has attracted much attention for high performance computing (HPC) since artificial intelligence (AI) accelerators surged. The technologies for heterogeneous integration, such as silicon interposer (2.5D), fan-out wafer-level-packaging (FOWLP), and organic substrate, have been proposed to integrate logic-logic or logic-HBM chips in the AI system for performance and cost benefits. However, the tremendous data flow in 5G era requires higher data rate and bandwidth for the extensive die-to-die communication. Therefore, a BEOL-scale re-distributed layer (RDL) technology should be developed to satisfy the requirements. In this paper, a novel ultra-high-density InFO (InFO_UHD) technology with submicron RDL is developed to provide high interconnect density and bandwidth for logic-logic system. The bandwidth density can achieve record high 10 Tbps/mm at line width and spacing (L/S) of 0.8/0.8 um and length of 500 um, for a logic-logic system using simplified IO driver. Using the technology in logic-memory system, we found that the scaling of RDL thickness, L/S, and dielectric thickness can mitigate ring-back problems in the eye diagram of organic substrate. Given HBM2 specification, the bandwidth density can achieve more than 0.4 Tbps/mm from dramatically improved signal integrity. Finally, power efficiency, in the metric of energy per bit, of the interconnect technology under simplified IO driver and HBM2 driver condition was calculated and compared with other technology, respectively.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"103 1","pages":"688-694"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72892954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Product Level Design Optimization for 2.5D Package Pad Cratering Reliability During Drop Impact 2.5D封装衬垫跌落冲击可靠性的产品级设计优化

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00323

Huayan Wang, Jing Wang, Jiefeng Xu, Van-Lai Pham, K. Pan, Seungbae Park, Hohyun Lee, G. Refai-Ahmed

{"title":"Product Level Design Optimization for 2.5D Package Pad Cratering Reliability During Drop Impact","authors":"Huayan Wang, Jing Wang, Jiefeng Xu, Van-Lai Pham, K. Pan, Seungbae Park, Hohyun Lee, G. Refai-Ahmed","doi":"10.1109/ECTC.2019.00323","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00323","url":null,"abstract":"The conversion from using tin-lead solder joint to lead-free solder joint has raised many pad cratering failures for electronics manufacturing. This phenomenon has become more severe to the 2.5D package which has a large heatsink attached on the top. The pad cratering issue has been found during testing, handling or transport due to a single overload. The package qualification process requires that it passes the board level drop test before shipping, however, this doesn't always guarantee that the package will survive from product level drop, especially for a complicated design product. Many types of research have been conducted to improve the package's board-level pad cratering reliability, few emphases were put on the product design. The aim of the present study is to evaluate several product design parameters with respect to PCB stress, using numerical methods. Several different design variables, such as reinforcement structure, heatsink size, pad design, were studied. Data are presented to show the effects of the above factors and to highlight the main factor to cause the pad cratering failure.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"37 1","pages":"2343-2348"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82537957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching 基于互连拼接的2.5D和3D小片的多片集成

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00278

Paul K. Jo, Ting Zheng, M. Bakir

引用次数: 1

Enhanced Performance of Laser-Assisted Bonding with Compression (LABC) Compared with Thermal Compression Bonding (TCB) Technology 激光辅助压缩键合(LABC)与热压缩键合(TCB)技术性能的比较

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00037

Kwang-Seong Choi, Y. Eom, Seok-Hwan Moon, Jiho Joo, leeseul Jeong, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim, G. Yoon, Kwang-Hee Lee, Chul-Hee Lee, Geun-Sik Ahn, Moo-Sup Shim

引用次数: 9

Electrochemical Impedance Spectroscopy (EIS) for Monitoring the Water Load on PCBAs Under Cycling Condensing Conditions to Predict Electrochemical Migration Under DC Loads 电化学阻抗谱(EIS)监测循环冷凝条件下pcba的水负荷以预测直流负载下的电化学迁移

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00084

S. Lauser, T. Richter, Verdingovas Vadimas, R. Ambat

{"title":"Electrochemical Impedance Spectroscopy (EIS) for Monitoring the Water Load on PCBAs Under Cycling Condensing Conditions to Predict Electrochemical Migration Under DC Loads","authors":"S. Lauser, T. Richter, Verdingovas Vadimas, R. Ambat","doi":"10.1109/ECTC.2019.00084","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00084","url":null,"abstract":"Humidity induced failures like metallic dendrite formation are a major problem for automotive electronic components. The harsh environment, where operating conditions in terms of temperature and humidity vary, can repeatedly provoke thin water layers on the surface of Printed Circuit Board Assemblies (PCBAs). The presence of a water film on electronics enables various corrosive processes. The understanding of the film formation and its effects is therefore crucial for assessing the humidity robustness of a specific setup. In this work, we conducted temperature and humidity load experiments with test boards containing interdigitated copper traces of different gap sizes on FR-4 substrate material. We repeatedly provoked condensation and evaporation conditions on the boards' surfaces by temperature cycling between 25 °C and 55 °C at 97 %rH. Electrochemical impedance spectroscopy (EIS) was employed as testing approach to detect the water film formation and respectively its evaporation. An AC excitation of 10 mV over a frequency range between 1 kHz and 100 kHz was used. Simultaneously, the commonly used SIR (Surface Insulation Resistance) test method was conducted at 5 V DC. This method lacks in delivering information on the actual water layer build up, but it detects the growth of dendrites, for which the DC voltage is required. The evaluated results of the EIS testing show, that the magnitude of water present can be depicted by the change in phase shift in the high frequency domain. We could also detect the water film closing for different gap sizes upon condensation. The DC measurements showed a correlation in terms of dendrite formation upon certain water load conditions.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"41 1","pages":"515-521"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84833907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Cu-Cu Bonding by Low-Temperature Sintering of Self-Healable Cu Nanoparticles 低温烧结自愈纳米铜的Cu-Cu键合研究

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00105

Junjie Li, Qi Liang, Chen Chen, T. Shi, G. Liao, Zirong Tang

{"title":"Cu-Cu Bonding by Low-Temperature Sintering of Self-Healable Cu Nanoparticles","authors":"Junjie Li, Qi Liang, Chen Chen, T. Shi, G. Liao, Zirong Tang","doi":"10.1109/ECTC.2019.00105","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00105","url":null,"abstract":"The Cu-Cu bonding temperature by using Cu nanoparticles is mainly influenced by the size and the purity of Cu nanoparticles. To remove the oxides of Cu, reducing atmosphere is always introduced into the sintering and bonding process. In this paper, a new Cu-Cu bonding method by sintering of self-healable Cu nanoparticles was proposed. With this method, the surface oxidation layer of Cu nanoparticle can be removed without reducing atmosphere at sintering and bonding process. In order to research the self-healing properties of the surface oxidized Cu nanoparticles, the sintering and bonding experiments were carried out under an Ar atmosphere. With self-healable Cu nanoparticles, the electrical resistivity of sintered Cu film can be reduced to lower than 5 µΩ·cm after sintering, and a high shear strength Cu-Cu joint over 25 MPa can be achieved after bonding at 250 °C. The oxygen content was also significantly reduced during the sintering and bonding process, which reflected the excellent self-healing property of Cu nanoparticle paste. The high Cu-Cu bonding strength and no requirement for reducing atmosphere indicate that the proposed self-healable Cu nanoparticle paste is promising to be wildly used in advanced electronics packaging.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"65 1","pages":"661-666"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90863091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Sub-10µm Pitch Hybrid Direct Bond Interconnect Development for Die-to-Die Hybridization 用于模对模杂交的10微米间距混合直接键合互连开发

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00103

John P. Mudrick, Jonatan A. Sierra-Suarez, M. Jordan, T. Friedmann, R. Jarecki, M. Henry

{"title":"Sub-10µm Pitch Hybrid Direct Bond Interconnect Development for Die-to-Die Hybridization","authors":"John P. Mudrick, Jonatan A. Sierra-Suarez, M. Jordan, T. Friedmann, R. Jarecki, M. Henry","doi":"10.1109/ECTC.2019.00103","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00103","url":null,"abstract":"Direct bond interconnect (DBI) processes enable chip to chip, low resistivity electrical connections for 2.5-D scaling of electrical circuits and heterogenous integration. This work describes SiO2/Cu DBI technology with Cu interconnect performance investigated over a range of inter-die Cu gap heights and post-bond annealing temperatures. Chemical mechanical polishing (CMP) generates wafers with a controlled Cu recess relative to the SiO2 surface, yielding die pairs with inter-die Cu gap heights ranging between 9 and 47 nm. Bonded die with different gap heights show similar per-connection resistance after annealing at 400 degrees Celsius but annealing at lower temperatures between 250 and 350 degrees Celsius results in failing or high-resistance interconnects with intermediate gaps showing lowest resistance. Cross-section scanning electron microscope (SEM) image analysis shows that the microstructure is largely independent of post-bond annealing temperature, suggesting that the temperature behavior is due to nanoscale scale interfacial effects not observable by SEM. The bond strength is affirmed by successful step-wise mechanical and chemical removal of the handle silicon layer to reveal metal from both die. This work demonstrates a 2.5-D integration method using a 3 micron Cu DBI process on a 7.5 micron pitch with electrical contacts ranging between 3.8 and 4.8 Ohms per contact plug.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"648-654"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90061349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4