Multilayer Glass Substrate with High Density Via Structure for All Inorganic Multi-chip Module

Abstract

Silicon interposer (Si-IP) technology has been used in accelerated processing units such as graphic processing units in high-performance computing because it can package a system-on-chip and high bandwidth memories. However, the conventional Si-IP has difficulty developing larger packages because of the mismatch in the coefficient thermal expansions (CTE) of the Si-IP and the organic substrate. Therefore, the Si-IP has limited capacity for improving computing performance by the application which requires more chips. We developed a multilayer glass substrate (Glass-ST) that features a stacked glass core and propose to apply this Glass-ST to a computer board. The proposed structure has no CTE mismatch and can use high density wiring. Thus, the Glass-ST enables the assembly of more large chips than is possible using the conventional Si-IP. In this study, we prepared a 100X100 mm Glass-ST with a 5/5 µm line/space and 20 µmΦ vias. We mounted nine 21X21 mm chips with 40 µm pitch micro bumps. The results revealed that conformal plated through glass vias and a fine wiring pattern had been fabricated in the Glass-ST, and that the nine chips and Glass-ST were connected by micro bumps. The maximum warpage of the nine chips was 23 µm between temperatures of 30°C and 250°C. This means that the Glass-ST can mount chips with micro bumps due to the very slight resulting warpage. In addition, we performed thermomechanical simulation to investigate the stress experienced by the micro bumps. The results show that the maximum stresses of micro bumps with pitches ranging between 10 µm and 55 um are very similar to that of 40 µm pitch micro bumps with which the real sample was packaged. We believe the improvements in the computing performance are significant by the Glass-ST technology compared to that of the conventional Si-IP technology.