Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching

Paul K. Jo, Ting Zheng, M. Bakir
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引用次数: 1

Abstract

This paper explores polylithic integration of heterogeneous dice (chiplets) for high-density electronic systems. In this approach, stitch-chips are used to enable 2.5D integration by providing dense signal pathways between assembled 'anchor chips,' while surface-embedded chips provide 3D face-to-face electrical interconnection with corresponding anchor chips. Multi-height Compressible MicroInterconnects (CMIs) are used to enable low-loss and mechanically robust interfaces between the anchor chips and the stitch-chips as well as the surface-embedded chips. Fabrication and assembly of a testbed is reported and demonstrates robust interconnection. In an effort to characterize the CMIs and stitch-chip channels at high-frequency, electromagnetic simulations are carried out and demonstrate less than 0.6 dB insertion loss for 90 µm tall CMIs and 500 µm long channels on a fused silica stitch-chip.
基于互连拼接的2.5D和3D小片的多片集成
本文探讨了高密度电子系统中异质晶片的多晶集成。在这种方法中,缝合芯片通过在组装的“锚定芯片”之间提供密集的信号通路来实现2.5D集成,而表面嵌入芯片则与相应的锚定芯片提供3D面对面的电互连。多高度可压缩微互连(CMIs)用于实现锚定芯片与缝合芯片以及表面嵌入芯片之间的低损耗和机械坚固接口。报告了测试平台的制作和组装,并证明了可靠的互连。为了在高频下表征cmi和缝片通道,进行了电磁模拟,并证明了在熔融硅缝片上90 μ m高的cmi和500 μ m长的通道的插入损耗小于0.6 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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