2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第5页

Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks 使用编码状态和统计协方差检查的卡尔曼滤波器并发错误检测和容错

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604691

Sujay Pandey, Suvadeep Banerjee, A. Chatterjee

{"title":"Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks","authors":"Sujay Pandey, Suvadeep Banerjee, A. Chatterjee","doi":"10.1109/IOLTS.2016.7604691","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604691","url":null,"abstract":"The Kalman filter is a versatile tool used in control and signal processing systems to predict statistically significant data from noisy measurements. In many practical control systems, not all the system states are directly controllable and observable. From noisy measurements of a limited subset of the observable system states, the Kalman filter predicts the mean values and covariances of the complete set of continuously evolving system states using specialized matrix arithmetic. Our goal is to detect errors in any underlying arithmetic computation (e.g. addition/multiplication) involved in the operation of the Kalman filter. While prior linear state checksum methods can be used to detect errors in a subset of the matrix operations of the Kalman filter, they do not suffice for detecting errors in the majority of calculations involved in determining the state covariances. To solve this problem, we develop the notion of statistical state covariance checks. Two applications of a Kalman filter, a trajectory tracking system and a linearized control system for an inverted pendulum are used to demonstrate the proposed approach. A simple state restoration approach is used to compensate for detected errors allowing the complete system to tolerate errors as and when they affect system operation.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"53 1","pages":"161-166"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75004428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

An on-line test solution for addressing interconnect shorts in on-chip networks 片上网络中互连短时间寻址的在线测试解决方案

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604660

B. Bhowmik, J. Deka, S. Biswas

引用次数: 9

REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture REMO:具有最小面积、功率、性能开销的冗余执行容错架构

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604681

Shoba Gopalakrishnan, Virendra Singh

引用次数: 12

Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices 航天FPGA器件鲁棒性评估的RTL故障模型比较

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604664

Romain Champon, V. Beroulle, Athanasios Papadimitriou, D. Hély, Gilles Genévrier, Frédéric Cézilly

引用次数: 5

ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors 现代微处理器地址转换机制的isa独立后硅验证

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604675

G. Papadimitriou, Athanasios Chatzidimitriou, D. Gizopoulos, Ronny Morad

{"title":"ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors","authors":"G. Papadimitriou, Athanasios Chatzidimitriou, D. Gizopoulos, Ronny Morad","doi":"10.1109/IOLTS.2016.7604675","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604675","url":null,"abstract":"Post-silicon validation complements traditional simulation-based pre-silicon verification and offers very high throughput since validation programs run at the speed of the actual hardware. Detection of bugs in the address translation subsystem of a microprocessor is much less straightforward than other hardware blocks because the address translation is an implicit process, which does not have an easily observable output to architecture or program visible locations. Validation of the correctness of the address translation mechanisms (ATMs) of microprocessors is both very important and challenging problem. In this paper, we present an ISA-independent methodology for the post-silicon validation of the ATMs in modern microprocessors. We first capture the effects of design bugs in address translation, by presenting actual bugs scenarios reported for commercial chips. We also describe an effective method for the detection of bugs in all address translation hardware blocks. The validation programs of the method are self-checking, i.e. do not require a bug-free model to compare with. Our experimental evaluation on Gem5 simulator shows the effectiveness of the methodology in detecting bugs in the address translation hardware of an x86-64 microprocessor model.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"63 1","pages":"72-77"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80678635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

RIIF-2: Toward the next generation reliability information interchange format RIIF-2:迈向下一代可靠性信息交换格式

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604693

A. Savino, S. Carlo, Alessandro Vallero, G. Politano, D. Gizopoulos, A. Evans

引用次数: 3

Advanced double-sampling architectures 先进的双采样架构

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604685

M. Nicolaidis, M. Dimopoulos

引用次数: 3

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode 耐变9T SRAM电路，具有鲁棒和低漏SLEEP模式

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604668

Hailong Jiao, Yongmin Qiu, V. Kursun

引用次数: 10

Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 2T和3T1D e-DRAM最小能量运行的统计分析与比较

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604667

Manish Rana, R. Canal, E. Amat, A. Rubio

引用次数: 3

NBTI aging evaluation of PUF-based differential architectures 基于puf的差分体系结构的NBTI老化评估

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604680

Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski

{"title":"NBTI aging evaluation of PUF-based differential architectures","authors":"Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski","doi":"10.1109/IOLTS.2016.7604680","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604680","url":null,"abstract":"Silicon Physical Unclonable Functions (PUFs) have emerged as novel cryptographic primitives, with the ability to generate unique chip identifiers and cryptographic keys by exploiting intrinsic manufacturing process variations. The “Two Choose One” PUF (TCO-PUF) has recently been proposed. It is based on a differential architecture and exploits the non-linear relationship between current and voltage in the subthreshold operating region. As CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) is becoming more pronounced, resulting in reliability issues for the PUF response. Differential design techniques can be useful for mitigating and canceling out first-order environmental dependencies such as aging, temperature and supply voltage. In this study, we investigate the robustness of PUFs with differential architectures, such as TCO-PUF and Arbiter-PUF, under the influence of NBTI. Our results indicate PUFs with differential architectures are less vulnerable to aging-related degradation compared to other PUF designs such as RO-PUF and SRAM-PUF. We show that the reliability of TCO-PUF and Arbiter-PUF only degrades by about 4.5% and 2.41%, respectively, after 10 years, while RO-PUFs and SRAM-PUFs degrade by about 12.76% in 10 years and 7% in 4.5 years, respectively.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"45 1","pages":"103-108"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73403300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12