2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第6页

Single-event performance of differential flip-flop designs and hardening implication 差分触发器设计的单事件性能及其加固意义

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604707

R. M. Chen, E. Zhang, B. Bhuva

引用次数: 0

STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation 基于stt - mtj的实时温度/电流变化补偿TRNG

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604694

E. Vatajelu, G. D. Natale, P. Prinetto

引用次数: 11

HLS-based sensitivity-inductive soft error mitigation for satellite communication systems 基于hls的卫星通信系统灵敏度感应软误差缓解

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604688

Xiang Chen, Wenhui Yang, Ming Zhao, Jing Wang

{"title":"HLS-based sensitivity-inductive soft error mitigation for satellite communication systems","authors":"Xiang Chen, Wenhui Yang, Ming Zhao, Jing Wang","doi":"10.1109/IOLTS.2016.7604688","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604688","url":null,"abstract":"Soft errors induced by space radiation environments seriously influence the reliability of spacecrafts in space and satellite communications, especially with ever shrinking geometries, higher-density circuits, and power saving techniques. Most of the existing soft error mitigation methods depend on triple modular redundancy (TMR) or dual-modular redundancy (DMR) to the original design target directly, which enlarge the resource overhead dramatically. In this paper, the high level synthesis (HLS) is considered to help to reduce the resource consumptions of TMR or DMR. By the HLS on node sensitivity, all design resources can be classified into three types: sensitive submodules, semi-sensitive sub-modules, and insensitive submodules. TMR can be applied for sensitive sub-modules to provide the highest reliability, while gate sizing can be applied for semi-sensitive sub-modules, which can help to mitigate the soft errors and to minimize the overhead introduced by the fault-tolerant techniques efficiently. In order to verify the effectiveness of the above proposal, appropriate scheduling schemes combined with the HLS are performed to an FIR filter. By simulations it is shown that, with the reduction of area relative to TMR over 60% for the FIR design, the reliability can reach over 99.9%.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"12 1","pages":"143-148"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86724844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Scalable FPGA graph model to detect routing faults 可扩展的FPGA图形模型来检测路由故障

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604690

L. Sterpone, G. Cabodi, S. Finocchiaro, C. Loiacono, F. Savarese, B. Du

引用次数: 1

Binary decision diagram to design balanced secure logic styles 二元决策图设计平衡的安全逻辑样式

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604710

Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede

{"title":"Binary decision diagram to design balanced secure logic styles","authors":"Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede","doi":"10.1109/IOLTS.2016.7604710","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604710","url":null,"abstract":"Embedded implementations of cryptographic algorithms require countermeasures against side-channel attacks (SCAs), that exploit physical variables measured during the computation. These countermeasures increase cost, power consumption and latency of the device. One class of countermeasures, hiding, consists of a balanced circuit style, including balancing of the capacitances and delays; it requires full connection to avoid memory effect that is an effect caused by repeatedly recharged energy after being only partially discharged at the internal parasitic capacitance. This paper proposes binary decision diagrams (BDDs) to derive complex pull-down networks that fulfill all these requirements while being compact at the same time; it uses sense amplifier-based logic (SABL) to obtain well-balanced pre-charge circuits. An attack based on mutual information analysis (MIA) is applied to the AES S-boxes implemented in our novel secure logic style. After the evaluation at pre-layout SPICE level, the balanced circuit with BDD leaks less information than comparable logic styles, even though the implementation area is reduced by 40.6%, the power consumption up to 46.1% and the delay by 35.2% compared to the classic SABL approach.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"104 1","pages":"239-244"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76012295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An soft error propagation analysis considering logical masking effect on re-convergent path 考虑再收敛路径上逻辑掩蔽效应的软误差传播分析

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604661

Shuhei Yoshida, Go Matsukawa, S. Izumi, H. Kawaguchi, M. Yoshimoto

引用次数: 1

SET response of a SEL protection switch for 130 and 250 nm CMOS technologies 用于130和250纳米CMOS技术的SEL保护开关的SET响应

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604695

M. Andjelković, A. Ilic, V. Petrovic, M. Nenadovic, Z. Stamenkovic, G. Ristić

引用次数: 1

Efficient fault tolerant parallel matrix-vector multiplications 高效容错并行矩阵向量乘法

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604665

Zhen Gao, P. Reviriego, J. A. Maestro

引用次数: 5

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection 对RTL故障模型行为建模，提高基于tsm的故障注入的置信度

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-01 DOI: 10.1109/IOLTS.2016.7604673

Jaime Espinosa, Carles Hernández, J. Abella

引用次数: 2

Susceptible workload driven selective fault tolerance using a probabilistic fault model 基于概率故障模型的易受影响工作负载驱动的选择性容错

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-05-05 DOI: 10.1109/IOLTS.2016.7604682

Mauricio D. Gutierrez, V. Tenentes, T. Kazmierski

{"title":"Susceptible workload driven selective fault tolerance using a probabilistic fault model","authors":"Mauricio D. Gutierrez, V. Tenentes, T. Kazmierski","doi":"10.1109/IOLTS.2016.7604682","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604682","url":null,"abstract":"In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"115-120"},"PeriodicalIF":0.0,"publicationDate":"2016-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80127997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5