2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献

Keytone: Silent Data Corruptions at Scale 关键字:无声的数据破坏的规模

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2023-07-03 DOI: 10.1109/iolts59296.2023.10224872

H. Dixit

引用次数: 0

Welcome 欢迎

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2022-11-10 DOI: 10.1109/IOLTS.2005.70

Yili Fu, Hesheng Wang, Yantao Shen

引用次数: 0

Field profiling & monitoring of payload transistors in FPGAs fpga中有效负载晶体管的现场分析与监测

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046215

Da Cheng, Amitava Majumdar, Xiaobao Wang, N. Chong

引用次数: 2

Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms 基于软件的错误检测机制的定时错误检测性能的硬件仿真相关性

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604677

Yutaka Masuda, M. Hashimoto, T. Onoye

{"title":"Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms","authors":"Yutaka Masuda, M. Hashimoto, T. Onoye","doi":"10.1109/IOLTS.2016.7604677","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604677","url":null,"abstract":"Software-based error detection techniques, which includes EDM (error detection mechanisms) transformation, are used for error localization in post-silicon validation. This paper evaluates the performance of EDM for timing error localization with 65-nm test chips assuming the following two EDM usage scenarios; (1) localizing a timing error occurred in the original program, and (2) localizing potential timing errors that vary execution results. Experimental results show that the EDM transformation customized for quick error detection detects 25% of timing errors in the original program in the first scenario and 56% of non-masked errors in the second scenario. However, these hardware measurement results are not consistent with the simulation results of our previous work. To investigate the reason, we focus on the following two differences between hardware and simulation; (1) design of power distribution network, and (2) definition of timing error occurrence frequency. We update the simulation setup for filling the difference and re-execute the simulation. We confirm that the simulation and the chip measurement results are consistent, which validates our simulation methodology.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"101 1","pages":"84-89"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75563457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Tackling long duration transients in sequential logic 处理顺序逻辑中的长时间瞬态

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604687

Erol Koser, W. Stechele

引用次数: 2

Resilient random modulo cache memories for probabilistically-analyzable real-time systems 用于概率分析实时系统的弹性随机模缓存存储器

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604666

David Trilla, Carles Hernández, J. Abella, F. Cazorla

引用次数: 4

Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks IEEE 1687网络故障诊断的自动生成激励

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604692

R. Cantoro, Mehrdad Montazeri, M. Reorda, Farrokh Ghani Zadegan, E. Larsson

{"title":"Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks","authors":"R. Cantoro, Mehrdad Montazeri, M. Reorda, Farrokh Ghani Zadegan, E. Larsson","doi":"10.1109/IOLTS.2016.7604692","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604692","url":null,"abstract":"The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, debug, calibration, etc.), by the use of configurable modules acting as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. Since the resulting networks could inevitably be affected by defects which may prevent their correct usage, solutions allowing not only to test against these defects, but also to diagnose them (i.e., to identify the location of possible faults) are of uttermost importance. This paper proposes a method to automatically generate suitable test stimuli: by applying them and observing the output of the network one can not only detect possible faults, but also identify the fault responsible for the misbehavior. Experimental results gathered on a set of benchmark networks with a prototypical tool implementing the proposed techniques show the feasibility and provide a first idea about the length of the required input stimuli.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"22 1","pages":"167-172"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77233099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

An efficient LDPC encoder architecture for space applications 用于空间应用的高效LDPC编码器架构

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604689

D. Theodoropoulos, N. Kranitis, A. Paschalis

{"title":"An efficient LDPC encoder architecture for space applications","authors":"D. Theodoropoulos, N. Kranitis, A. Paschalis","doi":"10.1109/IOLTS.2016.7604689","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604689","url":null,"abstract":"Quasi-Cyclic Low-Density Parity-Check Codes (QC-LDPC) have been recently adopted by the Consultative Committee for Space Data Systems (CCSDS) as recommended standard for channel coding in near-earth (C2) and deep-space (AR4JA) communications. Existing QC-LDPC encoder architectures proposed in the literature so far, are optimized for other standards (e.g. DVB-S2, IEEE 802.11e), but they are not suitable for efficient implementations for the specific CCSDS codes. In this paper, we introduce for the first time a novel encoder architecture, suitable for these codes. The architecture is a parallel implementation based on a series of recursive convolutional encoders and it leverages the inherent parallelism of generator's matrix QC structure to boost throughput performance. Furthermore, the generic definition of key encoder's parameters provides increased flexibility in terms of latency, FPGA resources and speed. In the special case of C2 code for near-earth communications, a novel architecture is introduced to efficiently handle the challenges arising from the generator's matrix circulant size (511 bits), which is not a power of 2. The proposed encoders operate on a continuous uninterrupted stream of input data and implement all the functions specified by CCSDS data-link layer protocols (i.e. framing, synchronization and randomization). The efficiency of the introduced architecture is demonstrated on a Xilinx XUPV5 development board, achieving multi-Gbps throughput and a significant speed-up when compared with existing approaches.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"17 1","pages":"149-154"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82595507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Hardware Trojans classification for gate-level netlists based on machine learning 基于机器学习的门级网络列表硬件木马分类

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604700

Kento Hasegawa, Masaru Oya, M. Yanagisawa, N. Togawa

{"title":"Hardware Trojans classification for gate-level netlists based on machine learning","authors":"Kento Hasegawa, Masaru Oya, M. Yanagisawa, N. Togawa","doi":"10.1109/IOLTS.2016.7604700","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604700","url":null,"abstract":"Recently, we face a serious risk that malicious third-party vendors can very easily insert hardware Trojans into their IC products but it is very difficult to analyze huge and complex ICs. In this paper, we propose a hardware-Trojan classification method to identify hardware-Trojan infected nets (or Trojan nets) using a support vector machine (SVM). Firstly, we extract the five hardware-Trojan features in each net in a netlist. Secondly, since we cannot effectively give the simple and fixed threshold values to them to detect hardware Trojans, we represent them to be a five-dimensional vector and learn them by using SVM. Finally, we can successfully classify a set of all the nets in an unknown netlist into Trojan ones and normal ones based on the learned SVM classifier. We have applied our SVM-based hardware-Trojan classification method to Trust-HUB benchmarks and the results demonstrate that our method can much increase the true positive rate compared to the existing state-of-the-art results in most of the cases. In some cases, our method can achieve the true positive rate of 100%, which shows that all the Trojan nets in a netlist are completely detected by our method.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"15 1","pages":"203-206"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82069878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 85

On the robustness of DCT-based compression algorithms for space applications 基于dct的空间压缩算法的鲁棒性研究

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604656

Serhiy Avramenko, M. Reorda, M. Violante, Görschwin Fey, Jan-Gerd Mess, R. Schmidt

引用次数: 4