Tackling long duration transients in sequential logic

Abstract

Single Event Transients (SETs) in combinational logic remain to be an important topic in the reliability domain. SETs were traditionally relatively short in comparison to the clock period. The majority of the countermeasures utilizes this property. However, advances in technology scaling will reverse the ratio. Investigations show that SETs may last up to multiple clock cycles in the future. So called Long Duration Transients (LDTs) corrupt almost all available countermeasures. This work presents a new methodology to tackle LDTs. Dual Modular Redundancy (DMR) is used to detect any corruption of the application logic. A new micro-rollback scheme is introduced, that expands DMR-Architectures with correction capabilities. The concept is also capable of handling single event upsets and timing violations. The scheme utilizes a newly designed History Cell. The History Cell introduces an area overhead of 74% and a power overhead of 106% compared to a standard cell D-flip-flop. Area and power overheads for expanding an existing DMR-Architecture with correction capabilities are approximately 24% and 28%, respectively.